Protection device for normally-on and normally-off high electron mobility transistors

• US 9,041,066 B2
• Filed: 10/16/2013
• Issued: 05/26/2015
• Est. Priority Date: 06/04/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Rieger, Walter, Hberlen, Oliver
• Primary Examiner(s): Montalvo, Eva Y
• Assistant Examiner(s): SYLVIA, CHRISTINA A
• Application Number:
  US14/054,918
• Publication Number:
  US 20140035003A1
• Time in Patent Office: 587 Days
• Field of Search: 257/191, 257/192, 257/194, 257/195, 257/E29.246, 257/E21.403, 257/E21.407
• US Class Current: 257/195
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A transistor device includes a compound semiconductor body, a normally-on high electron mobility field effect transistor (HEMT) formed in the compound semiconductor body and a protection device monolithically integrated in the same compound semiconductor body as the normally-on HEMT. The normally-on HEMT has a source, a drain, a gate, and a threshold voltage. The protection device has a source and a drain each shared with the normally-on HEMT, a gate and a positive threshold voltage that is less than a difference of the threshold voltage of the normally-on HEMT and a gate voltage used to turn off the normally-on HEMT. The protection device is operable to conduct current in a reverse direction when the normally-on HEMT is switched off. A transistor device including a normally-off HEMT and a monolithically integrated protection device is also provided.

Claims

1. A transistor device, comprising:

a compound semiconductor body;

a normally-on high electron mobility field effect transistor (HEMT) formed in the compound semiconductor body and having a source, a drain, a gate, and a threshold voltage; and

a protection device monolithically integrated in the same compound semiconductor body as the normally-on HEMT and having a source and a drain each shared with the normally-on HEMT, a gate and a positive threshold voltage that is less than a difference of the threshold voltage of the normally-on HEMT and a gate voltage used to turn off the normally-on HEMT, the protection device operable to conduct current in a reverse direction when the normally-on HEMT is switched off.

2. The transistor device of claim 1, wherein the gate of the normally-on HEMT is isolated from the compound semiconductor body by a first dielectric, the gate of the protection device is isolated from the compound semiconductor body by a second dielectric, and the first dielectric has a different thickness than the second dielectric.

3. The transistor device of claim 2, wherein the gate of the normally-on HEMT is disposed in a first trench extending into the compound semiconductor body, the gate of the protection device is disposed in a second trench extending into the compound semiconductor body, and the first trench extends to a different depth in the compound semiconductor body than the second trench.

4. The transistor device of claim 2, wherein the first dielectric and the second dielectric are formed from the same insulating layer.

5. The transistor device of claim 4, wherein the insulating layer comprises aluminum oxide, silicon nitride or silicon oxide.

6. The transistor device of claim 4, further comprising an additional insulating layer on the insulating layer.

7. The transistor device of claim 6, wherein the additional insulating layer comprises SiN, Zr oxide or Hf oxide.

8. The transistor device of claim 1, wherein the gate of the normally-on HEMT is disposed in a first trench extending into the compound semiconductor body, the gate of the protection device is disposed in a second trench extending into the compound semiconductor body, and the first trench extends to a different depth in the compound semiconductor body than the second trench.

9. The transistor device of claim 8, wherein the gate of the normally-on HEMT is isolated from the compound semiconductor body by a first dielectric, the gate of the protection device is isolated from the compound semiconductor body by a second dielectric, and the first dielectric has a different thickness than the second dielectric.

10. The transistor device of claim 1, wherein the gate of the normally-on HEMT contacts the compound semiconductor body and the gate of the protection device contacts the compound semiconductor body.

11. The transistor device of claim 1, wherein the normally-on HEMT and the protection device share a two-dimensional charge carrier gas channel region arising in the compound semiconductor body, and wherein the two-dimensional charge carrier gas channel region is disrupted between the normally-on HEMT and the protection device.

12. The transistor device of claim 11, further comprising an implanted region which disrupts the two-dimensional charge carrier gas channel region between the normally-on HEMT and the protection device.

13. A transistor device, comprising:

a compound semiconductor body;

a normally-off high electron mobility field effect transistor (HEMT) formed in the compound semiconductor body and having a source, a drain, a threshold voltage, and a p-doped III-nitride gate in contact with the compound semiconductor body; and

a protection device monolithically integrated in the same compound semiconductor body as the normally-off HEMT and having a source and a drain each shared with the normally-off HEMT, a gate and a threshold voltage less than the threshold voltage of the normally-off HEMT, the protection device operable to conduct current in a reverse direction when the normally-off HEMT is switched off.

14. The transistor device of claim 13, wherein the gate of the protection device is a p-doped III-nitride gate in contact with the compound semiconductor body.

15. The transistor device of claim 14, wherein the p-doped III-nitride gate of the normally-off HEMT and the p-doped III-nitride gate of the protection device each comprise p-doped GaN.

16. The transistor device of claim 14, wherein the p-doped III-nitride gate of the protection device has a lower p-doping concentration than the p-doped III-nitride gate of the normally-off HEMT.

17. The transistor device of claim 13, wherein the gate of the protection device comprises metal or poly-Si and is isolated from the compound semiconductor body by a dielectric.

18. The transistor device of claim 13, wherein the gate of the protection device is undoped or n-doped.

19. The transistor device of claim 13, wherein the normally-off HEMT and the protection device share a two-dimensional charge carrier gas channel region arising in the compound semiconductor body, and wherein the two-dimensional charge carrier gas channel region is disrupted between the normally-off HEMT and the protection device.

20. The transistor device of claim 19, further comprising an implanted region which disrupts the two-dimensional charge carrier gas channel region between the normally-off HEMT and the protection device.