Memory device and method for making same

• US 9,041,084 B2
• Filed: 06/24/2013
• Issued: 05/26/2015
• Est. Priority Date: 07/09/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Tilke, Armin
• Primary Examiner(s): Ingham, John C
• Application Number:
  US13/924,635
• Publication Number:
  US 20140154857A1
• Time in Patent Office: 701 Days
• Field of Search: 257/295, 257/E21.379, 257/E27.004
• US Class Current: 257/295
• CPC Class Codes: H01L 29/66242 Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H10B 63/32 of the bipolar type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

Embodiments relate to a method of forming a memory array, comprising: forming a collector layer; forming a plurality of collector regions in the collector layer; forming a plurality of base regions over the collector region; forming a plurality of emitter regions over the base regions; forming a plurality of memory elements over the emitter regions, wherein the collector regions, base regions and emitter regions form heterojunction bipolar transistors.

Claims

1. A method of forming a memory array that includes memory cells extending along a first direction and along a second direction, comprising:

forming a collector layer;

forming a plurality of collector regions in said collector layer, the collector regions being spaced apart from each other along said first direction and along said second direction;

forming a plurality of base regions over said collector region;

forming a plurality of emitter regions over said base regions; and

forming a plurality of memory elements over said emitter regions, wherein said collector regions, base regions and emitter regions form heterojunction bipolar transistors.

2. The method of claim 1, wherein forming said collector regions includes forming insulating trenches in said collector layer, said collector regions being spaced apart from each other by said insulating trenches.

3. The method of claim 2, wherein forming said base regions includes forming a base layer over said collector regions and over said insulating trenches using a differential epitaxial deposition.

4. The method of claim 3, wherein said differential epitaxial deposition forms monocrystalline regions over said collector regions and polycrystalline regions over said insulating trenches, said monocrystalline regions corresponding to said base regions.

5. The method of claim 4, further comprising, after forming said polycrystalline regions, doping said polycrystalline regions.

6. The method of claim 5, wherein said polycrystalline regions are doped by outdiffusion from said insulating trenches.

7. The method of claim 5, wherein polycrystalline regions are doped with boron.

8. The method of claim 3, further including forming insulating trenches in said base layer after forming said base regions.

9. The method of claim 1, wherein said collector regions comprise n-type material, said base regions comprise p-type material and said emitter regions comprise n-type material.

10. A method of forming a memory array, the method comprising:

forming a collector connection layer over a substrate;

forming a collector layer over the collector connection layer;

forming a plurality of insulating trenches, each insulating trench extending through the collector layer and into the collector connection layer thereby forming a plurality of collector regions in the collector layer;

forming a plurality of base regions over the collector region;

forming a plurality of emitter regions over the base regions; and

forming a plurality of memory elements over the emitter regions, wherein the collector regions, base regions and emitter regions form heterojunction bipolar transistors.

11. The method of claim 10, wherein the memory array includes memory cells extending along a first direction and along a second direction and wherein the collector regions are spaced apart from each other along the first direction and along the second direction.

12. The method of claim 10, wherein forming the base regions comprises forming a base layer over the collector regions and over the insulating trenches using a differential epitaxial deposition process.

13. The method of claim 12, wherein the differential epitaxial deposition process forms monocrystalline regions over the collector regions and polycrystalline regions over the insulating trenches, the monocrystalline regions corresponding to the base regions.

14. The method of claim 13, further comprising, after forming the polycrystalline regions, doping the polycrystalline regions.

15. The method of claim 14, wherein the polycrystalline regions are doped by outdiffusion from the insulating trenches.

16. A method of forming a memory array, the method comprising:

forming a plurality of memory cells arranged along a first direction and a second direction, each of the cells comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor, the heterojunction bipolar transistor of each of the memory cells including a collector region, the collector regions being spaced apart from each other along said first direction and along said second direction.

17. The method of claim 16, wherein the heterojunction bipolar transistor are formed by:

forming a collector layer;

forming the collector regions in the collector layer;

forming a plurality of base regions over the collector regions;

forming a plurality of emitter regions over the base regions; and

forming a plurality of memory elements over the emitter regions.

18. The method of claim 17, wherein forming the collector regions includes forming insulating trenches in the collector layer, the collector regions being spaced apart from each other by the insulating trenches.

19. The method of claim 18, wherein the collector layer overlies a collector connection layer and wherein each insulating trench extends through the collector layer and into the collector connection layer.

20. The method of claim 18, wherein forming the base regions comprises forming a base layer over the collector regions and over the insulating trenches using a differential epitaxial deposition that forms monocrystalline regions over the collector regions and polycrystalline regions over the insulating trenches, the monocrystalline regions corresponding to the base regions.