Nonvolatile memory structure

• US 9,041,089 B2
• Filed: 12/27/2013
• Issued: 05/26/2015
• Est. Priority Date: 06/07/2013
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Chen, Chih-Hsin, Chen, Wei-Ren, Lai, Tsung-Mu
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): Yang, Chi-Hua
• Application Number:
  US14/141,428
• Publication Number:
  US 20140361358A1
• Time in Patent Office: 515 Days
• Field of Search: 257/315, 257/298, 257/316, 365/185.14
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor.

Claims

1. A nonvolatile memory structure, comprising:

a semiconductor substrate of a first conductivity type having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row along a first direction, wherein the first, second, and third OD regions are separated from one another by an isolation region, and wherein the isolation region comprises a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region;

a first select transistor on the first OD region, wherein the first select transistor comprises a select gate extending along a second direction;

a floating gate transistor on the second OD region, wherein the floating gate transistor is serially coupled to the first select transistor, and wherein the floating gate transistor comprises a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions, wherein an entire perimeter of the floating gate is located directly on the isolation region; and

a second select transistor on the third OD region serially coupled to the floating gate transistor, wherein the second select transistor comprises a word line extending along the second direction.

2. The nonvolatile memory structure according to claim 1 wherein the first select transistor further comprises a source doping region of a second conductivity type coupled to a source line, an drain doping region of the second conductivity type spaced apart from the source doping region, a channel region between the source doping region and the drain doping region, the select gate overlying the channel region, and a gate dielectric layer between the select gate and the channel region, and the floating gate transistor is serially coupled to the first select transistor through the drain doping region.

3. The nonvolatile memory structure according to claim 1 wherein the first direction is substantially perpendicular to the second direction.

4. The nonvolatile memory structure according to claim 2 wherein a first well of the second conductivity type encompassing the first intervening isolation region and a second well of the second conductivity type encompassing the second intervening isolation region are provided in the semiconductor substrate, and the floating gate transistor is coupled to the drain doping region of the first select transistor through the first well that partially overlaps with the floating gate in the second OD region and partially overlaps with the drain doping region in the first OD region.

5. The nonvolatile memory structure according to claim 4 wherein the floating gate transistor is coupled to a source doping region of the second select transistor in the third OD region through the second well that partially overlaps with the floating gate in the second OD region and partially overlaps with the source doping region in the third OD region.

6. The nonvolatile memory structure according to claim 5 wherein the first well of the second conductivity type and the second well of the second conductivity type act as source/drain regions of the floating gate transistor.

7. The nonvolatile memory structure according to claim 6 wherein the first well and second well are both well-like structures and are formed prior to the formation of the floating gate.

8. The nonvolatile memory structure according to claim 5 wherein the second select transistor further comprise a drain doping region that is coupled to a bit line.

9. The nonvolatile memory structure according to claim 1 further comprising:

a fourth OD region and a fifth OD region, wherein the second OD region, the fourth OD region, and the fifth OD region are arranged in a column along the second direction; and

an extended portion of the floating gate that completely overlaps with the fourth OD region and the fifth OD region.

10. The nonvolatile memory structure according to claim 9 wherein the extended portion of the floating gate is capacitively coupled to a coupling gate region that overlaps with the fourth OD region and an erase gate region that overlaps with the fifth OD region.

11. The nonvolatile memory structure according to claim 9 wherein the fourth OD region and the fifth OD region are encompassed by one single ion well region having a conductivity type that is opposite to that of the semiconductor substrate.

12. The nonvolatile memory structure according to claim 9 wherein the fourth OD region and the fifth OD region are encompassed by two separate, space-apart ion well regions respectively, wherein the two separate, space-apart ion well regions both have a conductivity type that is opposite to that of the semiconductor substrate.

13. The nonvolatile memory structure according to claim 10 wherein the coupling gate region is defined by the fourth OD region which partially overlaps with a third well of the first conductivity type and a fifth well of the second conductivity type and the erase gate region is defined by the fifth OD region which partially overlaps with a fourth well of the first conductivity type and the fifth well of the second conductivity type.

14. A nonvolatile memory structure, comprising:

a semiconductor substrate of a first conductivity type having thereon a first oxide define (OD) region, a second OD region, a third OD region, a fourth OD region and a fifth OD region, wherein the first OD region, the second OD region, and the third OD region are arranged in a row along a first direction, while the second OD region, the fourth OD region, and the fifth OD region are arranged in a column along a second direction, wherein the first, second, and third OD regions are separated from one another by an isolation region, and wherein the isolation region comprises a first intervening isolation region between the first OD region and the second OD region, a second intervening isolation region between the second OD region and the third OD region, a third intervening isolation region between the second OD region and the fourth OD region, and a fourth intervening isolation region between the fourth OD region and the fifth OD region;

a first select transistor on the first OD region, wherein the first select transistor comprises a select gate extending along the second direction;

a floating gate transistor on the second OD region, wherein the floating gate transistor is serially coupled to the first select transistor, and wherein the floating gate transistor comprises a floating gate that is completely overlapped with underlying second OD region, the fourth OD region, the fifth OD region, the third intervening isolation region, and the fourth intervening isolation region, and is partially overlapped with the first and second intervening isolation regions, wherein an entire perimeter of the floating gate is located directly on the isolation region;

a sixth OD region being juxtaposed to the fourth OD region, wherein the sixth OD region is not overlapped with the floating gate;

a second select transistor coupled to a word line on the sixth OD region; and

wherein the floating gate transistor further comprises a heavily doped region of the first conductivity type formed in the third OD region that is electrically coupled to a bit line.

15. The nonvolatile memory structure according to claim 14 wherein the first select transistor further comprises a source doping region of the first conductivity type coupled to a source line, an drain doping region of the first conductivity type spaced apart from the source doping region, a channel region between the source doping region and the drain doping region, the select gate overlying the channel region, and a gate dielectric layer between the select gate and the channel region, and the floating gate transistor is serially coupled to the first select transistor through the drain doping region.

16. The nonvolatile memory structure according to claim 14 wherein the second select transistor further comprises a source doping region of the second conductivity type coupled to a program line, an drain doping region of the second conductivity type coupled to a well of the second conductivity type which overlaps the fourth OD region, a channel region between the source doping region and the drain doping region, a second select gate overlying the channel region, and a gate dielectric layer between the select gate and the channel region.

17. The nonvolatile memory structure according to claim 15 further comprising:

a seventh OD region being juxtaposed to the fifth OD region; and

an erase gate region capacitively coupled to an extended portion of the floating gate.

18. The nonvolatile memory structure according to claim 17 wherein a first well of the first conductivity type encompassing the first intervening isolation region and a second well of the first conductivity type encompassing the second intervening isolation region are provided in the semiconductor substrate.

19. The nonvolatile memory structure according to claim 18 wherein the erase gate region is defined by the fifth OD region which partially overlaps with a third well of the first conductivity type and a fourth well of the second conductivity type.

20. The nonvolatile memory structure according to claim 19 wherein the erase gate region is coupled to an erase line through the third well of the first conductivity type which partially overlaps the seventh OD region.

21. The nonvolatile memory structure according to claim 14 wherein a source/drain region of the floating gate transistor comprises a well-like structure and are formed prior to the formation of the floating gate.

22. The nonvolatile memory structure according to claim 17 wherein the first OD region, the second OD region, and the third OD region are encompassed by a first ion well of the second conductivity type, and wherein the fifth OD region and the seventh OD region are within a second ion well of the second conductivity type.

23. A nonvolatile memory structure, comprising:

a semiconductor substrate of a first conductivity type having thereon a first oxide define (OD) region, a second OD region, a third OD region, a fourth OD region and a fifth OD region, wherein the first, second, and third OD regions are separated from one another by an isolation region, and wherein the isolation region comprises a first intervening isolation region between the first OD region and the second OD region, a second intervening isolation region between the second OD region and the third OD region, a third intervening isolation region between the second OD region and the fourth OD region, and a fourth intervening isolation region between the fourth OD region and the fifth OD region;

a floating gate transistor on the second OD region, comprising a floating gate completely overlapped with underlying the second OD region and well-like structures that function as source/drain of the floating gate transistor, and wherein the floating gate further comprises an extended portion that completely overlaps with the fourth OD region and the fifth OD region, wherein an entire perimeter of the floating gate is located directly on the isolation region;

a coupling gate region in the semiconductor substrate, wherein the coupling gate region overlaps with the fourth OD region and is capacitively coupled to the extended portion of the floating gate; and

an erase gate region in the semiconductor substrate, wherein the erase gate region overlaps with the fifth OD region and is capacitively coupled to the extended portion of the floating gate;

wherein an entire perimeter of the floating gate is located directly on the isolation region.

24. The nonvolatile memory structure according to claim 23 further comprising:

a first select transistor on the first OD region, wherein the first select transistor comprises a select gate;

wherein the floating gate transistor is serially coupled to the first select transistor.

25. The nonvolatile memory structure according to claim 24 further comprising:

a sixth OD region being juxtaposed to the fourth OD region, wherein the sixth OD region is not overlapped with the floating gate; and

a second select transistor coupled to a word line on the sixth OD region.

26. The nonvolatile memory structure according to claim 24 further comprising:

a second select transistor serially coupled to the floating gate transistor on the third OD region, wherein the second select transistor comprises a second select gate.