Deeply depleted MOS transistors having a screening layer and methods thereof

• US 9,041,126 B2
• Filed: 09/05/2013
• Issued: 05/26/2015
• Est. Priority Date: 09/21/2012
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Hoffmann, Thomas, Shifren, Lucian, Thompson, Scott E., Ranade, Pushkar, Wang, Jing, Gregory, Paul E., Sonkusale, Sachin R., Scudder, Lance, Zhao, Dalong, Bakhishev, Teymur, Liu, Yujie, Wang, Lingquan, Zhang, Weimin, Pradhan, Sameer, Duane, Michael, Kim, Sung Hwan
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US14/019,187
• Publication Number:
  US 20140084385A1
• Time in Patent Office: 628 Days
• Field of Search: 257/402, 257/E29.054
• US Class Current: 257/402
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.

Claims

1. A semiconductor transistor structure formed on a silicon substrate, comprising:

a transistor gate on a top surface of the silicon substrate, the transistor gate having an effective gate length Lg, the transistor gate having two sides and a bottom with a bottom corner on each side defining a physical outer boundary of the gate;

a source and drain extension region on either side of the transistor gate extending a distance inward from each side of the transistor gate, the source and drain extension regions defining two inner edges that form the effective gate length Lg, the source and drain extension regions being doped with a predefined dopant polarity;

a deep source/drain doped region adjacent each of the source and drain extension regions, the deep source/drain doped regions being doped with a predefined dopant polarity that is the same as the dopant polarity for the source and drain extension regions, the deep source/drain doped regions having a dopant profile that includes a heavily doped portion therewithin;

wherein the source/drain doped region and the source and drain extension region on each side of the transistor gate are in electrical contact with each other, the location of the electrical contact forming an interface;

a substantially undoped channel portion that defines the space between the source and drain extension regions and the deep source/drain doped regions; and

a screening region comprising a highly doped region of opposite polarity from the polarity of the deep source/drain doped regions and the source and drain extension regions, the screening region being immediately below the substantially undoped channel portion, the screening region extending laterally between the deep source/drain doped regions, the screening region having a dopant concentration of 5×

10¹⁸ to 1×

10²⁰ atoms/cm³;

wherein the screening region is located a vertical depth below the substrate surface, the screening region being no closer to the gate than the interface and wherein the screening region is positioned to be either above or below the heavily doped portion of the deep source/drain doped regions;

and further including an outer portion defining a substantially undoped space region that substantially follows the combined shape of the deep source/drain doped regions and the source and drain extension regions, the outer portion having an outer edge that abuts the substantially undoped channel portion, the outer edge defining the interface, the screening region extending substantially to the outer edge of the outer portion.

2. The semiconductor transistor structure of claim 1, wherein the source and drain extension regions are raised above the surface level of the substrate.

3. The semiconductor transistor structure of claim 2, wherein the raised source and drain extension regions are formed using epitaxially grown silicon.

4. The semiconductor transistor structure of claim 1, wherein the source and drain extension regions and the deep source/drain doped regions form a shallow junction.

5. The semiconductor transistor structure of claim 1, further comprising:

a threshold voltage set region located immediately above the screening region, the threshold voltage set region being coextensive with and abutting the screening region.

6. The semiconductor transistor structure of claim 5, wherein both the threshold voltage set region and the screening region abut the deep source/drain doped regions.

7. The semiconductor transistor structure of claim 1, further including a concentration of germanium in the substantially undoped channel layer, the concentration of germanium sufficient to effect a widening of the Lg compared to the case of not using the concentration of germanium.

8. The semiconductor transistor structure of claim 7, wherein the concentration of germanium is introduced into the substantially undoped channel layer by way of ion implantation.

9. A semiconductor transistor structure formed on a silicon substrate, comprising:

a transistor gate formed by way of a starting point temporary dummy gate structure, the starting point temporary dummy gate structure having a first horizontal and first vertical dimension;

a source and drain extension doped region formed on each side of the temporary dummy gate structure using the temporary dummy gate structure as a mask, the source and drain extension doped regions being separated on each side of the temporary dummy gate structure by a first lateral distance and thereby defining an effective gate length Lg;

a final transistor gate formed after removing the temporary dummy gate structure, the final transistor gate having the first horizontal dimension but having a second vertical dimension, the second vertical dimension establishing a substantially horizontal bottom of the final transistor gate, the second vertical dimension achieved by forming a portion of the final transistor gate a vertical distance down into the silicon substrate;

a deep source and drain doped region adjacent each of the source and drain extension doped regions and separated from each other by a second lateral distance, the second lateral distance being greater than the first lateral distance, the deep source and drain doped regions extending a vertical distance into the silicon substrate, the deep source and drain doped regions having a substantially horizontal bottom;

wherein each of the source and drain extension doped regions and the deep source and drain doped regions are doped using dopants of a preselected polarity, the deep source and drain doped region and the source and drain extension doped region on each side of the transistor gate are in electrical contact with each other, the location of the electrical contact forming an interface; and

a highly doped screening region having a dopant concentration of about 5×

10¹⁸ to 1×

10²⁰ atoms/cm³, the highly doped screening region peak concentration point being located above the bottom of the deep source and drain doped region, the highly doped screening region being separated from the bottom of the final transistor gate by a substantially undoped channel layer, the highly doped screening region extending laterally between the deep source and drain doped region and having a finite thickness;

and further including an outer portion defining a substantially undoped space region that substantially follows the combined shape of the deep source and drain doped regions and the source and drain extension doped regions, the outer portion having an outer edge that abuts the substantially undoped channel portion, the outer edge defining the interface, the screening region extending substantially to the outer edge of the outer portion.

10. The semiconductor transistor structure of claim 9, further comprising:

a threshold voltage set region having a defined dopant concentration, the threshold voltage set region being located immediately above the highly doped screening region and extending laterally between the deep source and drain doped regions coextensive with the highly doped screening region, the threshold voltage set region being separated from the bottom of the final transistor gate by the substantially undoped channel layer.

11. The semiconductor transistor structure of claim 9, wherein the final transistor gate comprises a metal material.

12. The semiconductor transistor structure of claim 9, wherein the screening region is located from the bottom of the final transistor gate a distance of Lg/1.5 to Lg/5.

13. A semiconductor transistor structure formed in a silicon substrate, comprising:

a screening region in the silicon substrate, the screening region comprising a doped region that is of a defined thickness and extends laterally across the substrate, the screening region being doped with at least one dopant species effective to create a first polarity for the screening region, the screening region being doped to a dopant concentration of about 5×

10¹⁸ to 1×

10²⁰ atoms/cm³;

a substantially undoped channel portion that is directly above the screening region and effective to separate the screening region from the top surface of the silicon substrate;

a deep source/drain structure on either side of the screening region, the deep source/drain structure extending a defined depth that is deeper than the thickness of the screening region, the deep source/drain structure being doped with at least one dopant species effective to create a second polarity that is opposite of the first polarity; and

a doped upper portion extending to the top surface of the silicon substrate, the doped upper portion defining an effective gate length for the channel structure, the doped upper portion which may be angled inward, angled outward, be substantially vertical or follow a curved shape that adjoins the deep source/drain structure at an interface;

wherein the screening region is located to be laterally located either along the same plane as the interface or a distance below the interface, but not above the interface;

and further including an outer portion defining a substantially undoped space region that substantially follows the combined shape of the deep source/drain structure and doped upper portion, the outer portion having an outer edge that abuts the substantially undoped channel portion, the outer edge defining the interface, the screening region extending substantially to the outer edge of the outer portion.

14. The semiconductor transistor structure of claim 13, wherein the outer portion is made of undoped silicon germanium.

15. The semiconductor transistor structure of claim 13, wherein the deep source/drain structure is formed using epitaxial growth.

16. The semiconductor transistor structure of claim 13, further comprising:

a threshold voltage set region between the screening region and the undoped channel layer.

17. The semiconductor transistor structure of claim 13, wherein the screening region is formed using ion implantation.

18. The semiconductor transistor structure of claim 17, wherein the screening region is formed through a pre-formed ISSG oxide layer that is effective to create a screening region having a preselected depth, thickness, and dopant concentration.

19. The semiconductor transistor structure of claim 13, wherein the screening region is of a thickness of about 3 nm to 40 nm.