Logic chip including embedded magnetic tunnel junctions

• US 9,041,146 B2
• Filed: 03/15/2013
• Issued: 05/26/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Lee, Kevin J., Ghani, Tahir, Steigerwald, Joseph M., Epple, John H., Wang, Yih
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US13/994,716
• Publication Number:
  US 20140264679A1
• Time in Patent Office: 802 Days
• Field of Search: None
• US Class Current: 257/506
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/20 comprising components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.

Claims

1. An apparatus comprising:

a monolithic substrate;

a memory area, comprising (a) a magnetic tunnel junction (MTJ) that includes a tunnel barrier directly contacting lower and upper MTJ layers, located on the substrate; and

(b) an additional MTJ, having an additional tunnel barrier directly contacting additional lower and upper MTJ layers; and

a logic area located on the substrate;

wherein a horizontal plane, which is parallel to the tunnel barrier, intersects the MTJ and the additional MTJ, a first Inter-Layer Dielectric (ILD) material included in the memory area, and a second ILD material included in the logic area;

wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer sidewall by a horizontal offset space that defines a horizontal offset distance;

wherein a contiguous etch stop portion directly contacts the MTJ and the additional MTJ.

2. The apparatus of claim 1 comprising a spacer, having a width equal to the horizontal offset distance, directly contacting the upper MTJ layer and the tunnel barrier.

3. The apparatus of claim 2 further comprising a hardmask directly contacting an upper surface of the upper MTJ layer and the spacer.

4. The apparatus of claim 1 wherein the horizontal plane intersects the etch stop material.

5. The apparatus of claim 2 wherein the horizontal plane intersects the etch stop material and the etch stop material directly contacts an upper surface of the spacer.

6. The apparatus of claim 1, wherein:

the first ILD material includes at least one of silicon oxide, silicon oxynitride, porous silicon oxide, fluorinated silicon oxide, carbon-doped oxide, porous carbon-doped oxide, polyimide, polynorbornene, benzocyclobutene, flowable oxide, and polytetrafluoroethylene and the second ILD material includes an additional at least one of silicon oxide, silicon oxynitride, porous silicon oxide, fluorinated silicon oxide, carbon-doped oxide, porous carbon-doped oxide, polyimide, polynorbornene, benzocyclobutene, flowable oxide, and polytetrafluoroethylene; and

the first bottom MTJ includes sublayers comprising at least one of tantalum, platinum manganese;

cobalt iron;

Ruthenium (Ru); and

cobalt iron boron.

7. The apparatus of claim 1, wherein the logic area is included in a processor and the memory area includes a memory that is a spin torque transfer magnetoresistive random access memory (STT-MRAM).

8. The apparatus of claim 1, wherein at least one of the first upper MTJ layer, first lower MTJ layer, and first tunnel barrier includes sublayers.

9. The apparatus of claim 1 wherein the contiguous etch stop portion directly contacts the first ILD.

10. The apparatus of claim 1, wherein the first ILD material is adjacent the MTJ, the first and second ILD materials are unequal to one another, and the first and second ILDs directly contact one another.

11. An apparatus comprising:

a monolithic substrate;

a memory area, comprising a magnetic tunnel junction (MTJ) that includes a tunnel barrier directly contacting lower and upper MTJ layers, located on the substrate; and

a logic area located on the substrate;

wherein a horizontal plane, which is parallel to the tunnel barrier, intersects the MTJ, a first Inter-Layer Dielectric (ILD) material included in the memory area, and a second ILD material included in the logic area and unequal to the first ILD material;

wherein the horizontal plane intersects etch stop material included between the MTJ and the first ILD material.

12. The apparatus of claim 11 wherein the etch stop material directly contacts at least one of the tunnel barrier and the lower MTJ layer.

13. The apparatus of claim 11 wherein the etch stop material is included in an etch stop layer having directly connected horizontal and vertical lengths that both directly contact the first ILD material.

14. The apparatus of claim 11 wherein the etch stop material is included in an etch stop layer that extends from the memory area into the logic area.

15. An apparatus comprising:

a first magnetic tunnel junction (MTJ) including a first upper MTJ layer, a first lower MTJ layer, and a first tunnel barrier directly contacting a first lower surface of the first upper MTJ layer and a first upper surface of the first lower MTJ layer;

a memory area, including the first MTJ, and a logic area on a monolithic substrate;

wherein the first upper MTJ layer includes a first upper MTJ layer sidewall and the first lower MTJ layer includes a first lower MTJ sidewall horizontally offset from the first upper MTJ layer sidewall by a first horizontal offset space that defines a first horizontal offset distance;

wherein a first spacer, having a width equal to the first horizontal offset distance, directly contacts the first upper MTJ layer and the first tunnel barrier;

wherein a first horizontal plane, parallel to the first lower surface of the first upper MTJ layer, intersects the first MTJ, a first ILD material adjacent the first MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another;

wherein the first horizontal plane intersects a first polish stop material included between the first MTJ and the first ILD material.

16. The apparatus of claim 15 further comprising a first hardmask directly contacting a first upper surface of the first upper MTJ layer and the first spacer.

17. The apparatus of claim 16, wherein the first ILD material includes flowable oxide and the second ILD material includes at least one of silicon oxide, porous silicon oxide, fluorinated silicon oxide, carbon-doped oxide, porous carbon-doped oxide, polyimide, polynorbornene, benzocyclobutene, and polytetrafluoroethylene.

18. An apparatus comprising:

a monolithic substrate;

a memory area, comprising a magnetic tunnel junction (MTJ) that includes a tunnel barrier directly contacting lower and upper MTJ layers, located on the substrate;

a logic area located on the substrate;

a spacer, having a width equal to a horizontal offset distance, directly contacting the upper MTJ layer and the tunnel barrier; and

a hardmask directly contacting an upper surface of the upper MTJ layer and the spacer;

wherein a horizontal plane, which is parallel to the tunnel barrier, intersects the MTJ, a first Inter-Layer Dielectric (ILD) material included in the memory area, and a second ILD material included in the logic area;

wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer sidewall by a horizontal offset space that defines the horizontal offset distance.

19. The apparatus of claim 18, wherein the logic area is included in a processor and the memory area includes a memory that is a spin torque transfer magnetoresistive random access memory (STT-MRAM).

20. The apparatus of claim 18 wherein the horizontal plane intersects etch stop material included between the MTJ and the first ILD material;

and the etch stop material is included in an etch stop layer that directly contacts the hardmask.

21. The apparatus of claim 18 wherein the horizontal plane intersects etch stop material included between the MTJ and the first ILD material;

and the etch stop material is included in an etch stop layer that directly contacts an upper surface of the spacer.

22. The apparatus of claim 18 comprising etch stop material that directly contacts at least one of the tunnel barrier and the lower MTJ layer.

23. The apparatus of claim 18 comprising etch stop material included in an etch stop layer having directly connected horizontal and vertical lengths that both directly contact the first ILD material.

24. The apparatus of claim 18 comprising etch stop material included in an etch stop layer that extends from the memory area into the logic area.