Inductor with magnetic material

• US 9,041,152 B2
• Filed: 07/03/2013
• Issued: 05/26/2015
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Luo, Cheng-Wei, Yen, Hsiao-Tsung, Kuo, Chin-Wei, Jeng, Min-Chie
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US13/935,238
• Publication Number:
  US 20140264734A1
• Time in Patent Office: 692 Days
• Field of Search: 257/531, 257/659, 257/773, 257/774, 257/779, 257/E23.114, 438/125
• US Class Current: 257/531
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 2017/0066 with a magnetic layer
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate inductors for integrated circuits H01L28/10
• CPC Class Codes: H01F 2027/2809 on stacked layers
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.

Claims

1. A semiconductor device, comprising:

a semiconductor die comprising a first metallization layer, the first metallization layer comprising a first conductive pattern;

an interposer comprising a second metallization layer, the second metallization layer comprising a second conductive pattern; and

conductive bumps bonding the semiconductor die to the interposer, some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a single coil, the coil having a magnetic layer positioned within, the magnetic layer being interposed between the first metallization layer and the second metallization layer.

2. The semiconductor device of claim 1, wherein the first conductive pattern and the second conductive pattern each comprises at least two trace links, wherein the at least two trace links of one of the first conductive pattern and the second conductive pattern are transverse links each coupling a respective adjacent pair of the at least two trace links of the other of the first conductive pattern and the second conductive pattern.

3. The semiconductor device of claim 1, wherein the first conductive pattern and the second conductive pattern each comprises a ring-shape of conductive materials.

4. The semiconductor device of claim 1, wherein the interposer further comprises a substrate upon which is the second metallization layer, and the interposer further comprises a through substrate via penetrating through the substrate, the through substrate via being electrically coupled to the second conductive pattern.

5. The semiconductor device of claim 1, wherein:

the semiconductor die further comprises a third metallization layer, the first metallization layer being on the third metallization layer, wherein the third metallization layer comprises a third conductive pattern, and

the interposer further comprises a fourth metallization layer, the second metallization layer being on the fourth metallization layer, wherein the fourth metallization layer comprises a fourth conductive pattern, wherein the third conductive pattern is electrically coupled to the fourth conductive pattern to form an outer coil surrounding the coil, the coil being an inner coil.

6. The semiconductor device of claim 1, further comprising:

a substrate in the interposer, the second metallization layer being on a surface of the substrate opposite the semiconductor die; and

through substrate vias extending through the substrate, the through substrate vias electrically coupling the first conductive pattern to the second conductive pattern.

7. An interposer, comprising:

a substrate;

a first metallization layer on a first side of the substrate, the first metallization layer comprising a first conductive pattern;

a second metallization layer on the first metallization layer, the second metallization layer comprising a second conductive pattern;

a third metallization layer on a second side of the substrate, the second side being opposite the first side, the third metallization layer comprising a third conductive pattern;

a fourth metallization layer on the third metallization layer, the fourth metallization layer comprising a fourth conductive pattern;

through substrate vias (TSVs) extending through the substrate, wherein at least one TSV electrically couples one of the first conductive pattern and the second conductive pattern to one of the third conductive pattern and the fourth conductive pattern to form a first coil, and at least one other TSV electrically couples one of the first conductive pattern and the second conductive pattern to one of the third conductive pattern and fourth conductive pattern to form a second coil; and

a magnetic layer within at least one of the first coil and the second coil.

8. The interposer of claim 7, wherein the first conductive pattern, the second conductive pattern, the third conductive pattern, and the fourth conductive pattern each comprises at least two trace links, wherein the at least two trace links of each of the first conductive pattern and the second conductive pattern are transverse traces, wherein the at least one TSV electrically couples the first conductive pattern to the one of the third conductive pattern and the fourth conductive pattern, and wherein the at least one other TSV electrically couples the second conductive pattern to the other of the third conductive pattern and the fourth conductive pattern.

9. The interposer of claim 8, wherein the at least one TSV electrically couples the first conductive pattern to the third conductive pattern, and wherein the at least one other TSV electrically couples the second conductive pattern to the fourth conductive pattern.

10. The interposer of claim 7, wherein the first conductive pattern and the third conductive pattern each comprises a ring-shape, wherein the at least one TSV electrically couples the first conductive pattern to the third conductive pattern, and wherein the at least one other TSV electrically couples the first conductive pattern to the third conductive pattern.

11. The interposer of claim 10, wherein the second conductive pattern and the fourth conductive pattern each comprises a cross link.

12. The interposer of claim 7, wherein the first coil is an inner coil surrounded by the second coil.

13. A semiconductor device, comprising:

a first substrate having a first conductive pattern formed thereon;

a second substrate having a second conductive pattern formed thereon;

conductive elements electrically coupling the first portion and the second portion; and

a first magnetic layer interposed between the first conductive pattern and the second conductive pattern, the conductive elements, the first portion, and the second portion forming a first coil around at least a portion of the first magnetic layer.

14. The semiconductor device of claim 13, wherein the first magnetic layer directly contacts the first conductive pattern.

15. The semiconductor device of claim 13, wherein the conductive elements comprise solder bumps.

16. The semiconductor device of claim 13, further comprising a second magnetic layer on the first conductive pattern.

17. The semiconductor device of claim 16, wherein the second magnetic layer extends along sidewalls of the first conductive pattern.

18. The semiconductor device of claim 16, further comprising a third magnetic layer on the second conductive pattern.

19. The semiconductor device of claim 18, wherein the third magnetic layer extends along sidewalls of the second conductive pattern.

20. The semiconductor device of claim 13, wherein the first conductive pattern is formed in a dielectric layer, the first magnetic layer extending over the first conductive pattern and the dielectric layer.