Semiconductor device for battery control and battery pack

• US 9,041,358 B2
• Filed: 03/02/2013
• Issued: 05/26/2015
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kato, Daisuke, Enomoto, Ryosuke
• Primary Examiner(s): Rodas, Richard Isla
• Assistant Examiner(s): PELTON, NATHANIEL R
• Application Number:
  US13/783,240
• Publication Number:
  US 20130257379A1
• Time in Patent Office: 815 Days
• Field of Search: 320/128, 320/134, 320/136, 320/137
• US Class Current: 320/134
• CPC Class Codes: G01R 31/388 involving voltage measurements
• CPC Class Codes: H01L 25/00 Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01M 10/4257 Smart batteries, e.g. electronic circuits inside the housing of the cells or batteries
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02J 7/00034 Charger exchanging data with an electronic device, i.e. telephone, whose internal battery is under charge
• CPC Class Codes: H02J 7/00302 Overcharge protection
• CPC Class Codes: H02J 7/00304 Overcurrent protection
• CPC Class Codes: H02J 7/00306 Overdischarge protection
• CPC Class Codes: H02J 7/00308 Overvoltage protection
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A semiconductor device for battery control includes a CPU, a first bus coupled to the CPU, a second bus not coupled to the CPU, and a protective function circuit for protecting a battery from stress applied thereto. The semiconductor device also includes a non-volatile memory storing trimming data, a trimming circuit to perform trimming required to allow the protective function circuit to exert a protective function, and a bus control circuit capable of selectively coupling the first bus and the second bus to the non-volatile memory. The semiconductor device further includes a transfer logic circuit which causes, by making the bus control circuit select the second bus, a trimming data transfer path leading from the non-volatile memory to the trimming circuit to be formed and the trimming data stored in the non-volatile memory to be transferred to the trimming circuit without involving the CPU.

Claims

1. A semiconductor device for battery control comprising:

a CPU;

a first bus coupled to the CPU;

a second bus not coupled to the CPU;

a protective function circuit for protecting a battery from stress applied thereto;

a non-volatile memory storing trimming data;

a trimming circuit to perform trimming required to allow the protective function circuit to exert a protective function;

a bus control circuit capable of selectively coupling the first bus and the second bus to the non-volatile memory, and

a transfer logic circuit which causes, by making the bus control circuit select the second bus, a trimming data transfer path leading from the non-volatile memory to the trimming circuit to be formed and the trimming data stored in the non-volatile memory to be transferred to the trimming circuit without involving the CPU,

wherein, in accordance with the trimming data received via the second bus, the trimming circuit performs trimming required to allow the protective function circuit to exert a protective function.

2. The semiconductor device for battery control according to claim 1,

wherein the non-volatile memory includes a first storage area accessible by a user of the semiconductor device for battery control and a second storage area not accessible by the user, and

wherein the trimming data is stored in the second storage area.

3. The semiconductor device for battery control according to claim 2,

wherein the transfer logic circuit asserts a transfer completion signal after having the trimming data in the non-volatile memory transferred to the trimming circuit via the second bus, and

wherein the CPU is activated after the transfer completion signal is asserted.

4. The semiconductor device for battery control according to claim 3, wherein the trimming circuit includes;

a first trimming circuit for trimming, in accordance with the trimming data, a first reference voltage which is referred to for overvoltage detection during charging of the battery;

a second trimming circuit for trimming, in accordance with the trimming data, a second reference voltage which is referred to for overcurrent detection during charging of the battery;

a third trimming circuit for trimming, in accordance with the trimming data, a third reference voltage which is referred to for discharge overvoltage detection during discharging of the battery,

a fourth trimming circuit for trimming, in accordance with the trimming data, a fourth reference voltage which is referred to for short-circuit detection during discharging of the battery;

a fifth trimming circuit for trimming, in accordance with the trimming data, a voltage dividing ratio of a voltage dividing resistor for overvoltage detection during charging of the battery, and

a sixth trimming circuit for trimming, in accordance with the trimming data, a voltage dividing ratio of a voltage dividing resistor for discharge overvoltage detection during discharging of the battery.

5. The semiconductor device for battery control according to claim 4, wherein the trimming circuit further includes a seventh trimming circuit for trimming, in accordance with the trimming data, a time required to determine overvoltage detection during charging of the battery, a time required to determine overcurrent detection during charging of the battery, a time required to determine discharge overvoltage detection during discharging of the battery, and a time required to determine short-circuit detection during discharging of the battery.

6. The semiconductor device for battery control according to claim 5, wherein, based on a power-on reset signal generated when a voltage supply from the battery is started, the transfer logic circuit causes, by making the bus control circuit select the second bus, a trimming data transfer path leading from the non-volatile memory to the trimming circuit to be formed and the trimming data stored in the non-volatile memory to be transferred to the trimming circuit without involving the CPU.

7. A semiconductor device for battery control comprising:

a MOS transistor coupled in series to a battery;

a CPU capable of controlling the MOS transistor;

a first bus coupled to the CPU;

a second bus not coupled to the CPU;

a protective function circuit for protecting the battery from stress applied thereto;

a non-volatile memory storing trimming data;

a trimming circuit to perform trimming required to allow the protective function circuit to exert a protective function;

a bus control circuit capable of selectively coupling the first bus and the second bus to the non-volatile memory, and

a transfer logic circuit which causes, by making the bus control circuit select the second bus, a trimming data transfer path leading from the non-volatile memory to the trimming circuit to be formed and the trimming data stored in the non-volatile memory to be transferred to the trimming circuit without involving the CPU;

wherein, in accordance with the trimming data received via the second bus, the trimming circuit performs trimming required to allow the protective function circuit to exert a protective function.

8. A battery pack including a chargeable battery and a semiconductor device for battery control which can control charging of the battery, the semiconductor device for battery control comprising:

a MOS transistor coupled in series to the battery;

a CPU capable of controlling the MOS transistor;

a first bus coupled to the CPU;

a second bus not coupled to the CPU;

a protective function circuit for protecting the battery from stress applied thereto;

a non-volatile memory storing trimming data;

a trimming circuit to perform trimming required to allow the protective function circuit to exert a protective function;

a bus control circuit capable of selectively coupling the first bus and the second bus to the non-volatile memory, and

a transfer logic circuit which causes, by making the bus control circuit select the second bus, a trimming data transfer path leading from the non-volatile memory to the trimming circuit to be formed and the trimming data stored in the non-volatile memory to be transferred to the trimming circuit without involving the CPU,

wherein, in accordance with the trimming data received via the second bus, the trimming circuit performs trimming required to allow the protective function circuit to exert a protective function.