Operational time extension

• US 9,041,430 B2
• Filed: 01/28/2014
• Issued: 05/26/2015
• Est. Priority Date: 12/01/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Rohe, Andre, Teig, Steven, Schmit, Herman, Redgrave, Jason, Caldwell, Andrew
• Primary Examiner(s): WHITE, DYLAN C
• Application Number:
  US14/166,680
• Publication Number:
  US 20140240001A1
• Time in Patent Office: 483 Days
• Field of Search: 326/47, 716/108, 365/189.08
• US Class Current: 326/38
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

An integrated circuit (IC) with a novel configurable routing fabric is provided. The configurable routing fabric has signal paths that propagate signals between user registers on user clock cycles. Each signal path includes a set of configurable storage elements and a set of configurable logic elements. Each configurable storage element in the path is reconfigurable on every sub-cycle of the user clock cycle to either store an incoming signal or to pass the incoming signal transparently.

Claims

1. An integrated circuit (IC) comprising:

a first user register and a second user register, wherein the first and second user registers operate on a user clock; and

a path for propagating signals from the first user register to the second user register in one user clock cycle, the path comprising a set of configurable storage elements and a set of configurable logic elements, wherein each configurable storage element is reconfigurable on every sub-cycle of the user clock cycle to store an incoming signal or to pass the incoming signal transparently, wherein each user clock cycle comprises N sub-cycles.

2. The IC of claim 1, wherein each configurable storage element is a latch.

3. The IC of claim 1, wherein the path propagates a particular signal from the first user register to the second user register through M signal-storing configurable storage elements.

4. The IC of claim 3, wherein M is an integer less than N.

5. The IC of claim 3, wherein at least one of the M configurable storage elements passes the propagated signal transparently.

6. The IC of claim 1, wherein a first configurable storage element in the path stores the particular signal before propagating the stored signal to a second configurable storage element in the path, wherein the second configurable storage element stores the propagated signal from the first configurable storage element at least two sub-cycles after the first configurable storage element stores the particular signal.

7. The IC of claim 6, wherein the particular signal is propagated from the first configurable storage element to the second configurable storage element without an intervening configurable storage element.

8. The IC of claim 1, wherein a first configurable storage element in the path stores the particular signal before propagating the stored signal to a second configurable storage element in the path, wherein the particular signal is propagated from the first configurable storage element to the second configurable storage element through a third configurable storage element that is configured to pass the propagated signal transparently.

9. A method comprising:

at an integrated circuit (IC), producing a particular signal at a first user register at a first user clock cycle;

propagating the particular signal through a path from the first user register to a second user register, wherein the path comprises a set of configurable storage elements and a set of configurable logic elements, wherein each configurable storage element is reconfigurable on every sub-cycle of the user clock cycle to store an incoming signal or to pass the incoming signal transparently, wherein each user clock cycle comprises N sub-cycles; and

storing the propagated particular signal at the second user register at a second user clock cycle.

10. The method of claim 9, wherein each configurable storage element is a latch.

11. The method of claim 9, wherein the path is configured to propagate the particular signal from the first user register to the second user register through M signal-storing configurable storage elements.

12. The method of claim 11, wherein M is an integer less than N.

13. The method of claim 11, wherein at least one of the M configurable storage elements is configured to pass the propagated signal transparently.

14. The method of claim 11, wherein a first configurable storage element in the path stores the particular signal before propagating the stored signal to a second configurable storage element in the path, wherein the particular signal is propagated from the first configurable storage element to the second configurable storage element through a third configurable storage element that is configured to pass the propagated signal transparently.

15. The method of claim 9, wherein a first configurable storage element in the path stores the particular signal before propagating the stored signal to a second configurable storage element in the path, wherein the second configurable storage element stores the propagated signal from the first configurable storage element at least two sub-cycles after the first configurable storage element stores the particular signal.

16. The method of claim 15, wherein the particular signal is propagated from the first configurable storage element to the second configurable storage element without an intervening configurable storage element.

17. A non-transitory computer-readable medium storing a computer program for configuring an integrated circuit (IC), the computer program executable by at least one processor, the computer program comprising sets of instructions for:

configuring a first user register to produce a particular signal at a first user clock cycle;

configuring a path for propagating the particular signal from the first user register to a second user register, wherein the path comprises a set of configurable storage elements and a set of configurable logic elements, wherein each configurable storage element is reconfigurable on every sub-cycle of the user clock cycle to store an incoming signal or to pass the incoming signal transparently, wherein each user clock cycle comprises N sub-cycles; and

configuring the second user register to store the propagated particular signal at a second user clock cycle.

18. The non-transitory computer-readable medium of claim 17, the program further comprising sets of instructions for:

configuring a first configurable storage element in the path to store the particular signal before propagating the stored signal to a second configurable storage element in the path; and

configuring the second configurable storage element to store the propagated signal from the first configurable storage element at least two sub-cycles after the first configurable storage element stores the particular signal.

19. The non-transitory computer-readable medium of claim 18, wherein the particular signal is propagated from the first configurable storage element to the second configurable storage element without an intervening configurable storage element.

20. The non-transitory computer-readable medium of claim 17, the program further comprising sets of instructions for:

configuring a first configurable storage element in the path to store the particular signal before propagating the stored signal to a second configurable storage element in the path; and

configuring a third configurable storage element to pass the propagated signal transparently when the particular signal is propagated from the first configurable storage element to the second configurable storage element through the third configurable storage element.