Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods
First Claim
1. A three-dimensional (3D) flip-flop, comprising:
- a master latch disposed in a first tier of a 3D integrated circuit (IC) (3DIC), the master latch configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output;
at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output; and
at least one monolithic intertier via (MIV) coupling the master latch output to an input of the at least one slave latch.
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Abstract
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.
121 Citations
20 Claims
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1. A three-dimensional (3D) flip-flop, comprising:
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a master latch disposed in a first tier of a 3D integrated circuit (IC) (3DIC), the master latch configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output; at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output; and at least one monolithic intertier via (MIV) coupling the master latch output to an input of the at least one slave latch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A three-dimensional (3D) flip-flop, comprising:
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a master means for latching disposed in a first tier of a 3D integrated circuit (IC) (3DIC), the master means for latching configured to receive a flip-flop input and a clock input and the master means configured to provide a master latch output; at least one slave means for latching disposed in at least one additional tier of the 3DIC, the at least one slave means for latching configured to provide a 3DIC flip-flop output; and at least one monolithic intertier via (MIV) coupling the master latch output to an input of the at least one slave means. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method of forming a three-dimensional (3D) integrated circuit (IC) (3DIC), comprising:
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providing a master latch on a first tier of the 3DIC; providing a slave latch on a second tier of the 3DIC wherein the second tier is different from the first tier; and coupling the master latch to the slave latch with at least one monolithic intertier via (MIV). - View Dependent Claims (16, 17, 18, 19, 20)
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Specification