Circuit and method of clocking multiple digital circuits in multiple phases
First Claim
1. A circuit comprising:
- a power supply terminal;
a clock parsing circuit configured to produce multiple clock signals having different phases;
a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal, each digital circuit including an input to receive data and logic to process the data, each digital circuit responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the power supply terminal to process the data to produce a data output;
a control circuit coupled to the clock parsing circuit and the plurality of digital circuits, the control circuit to selectively control the clock parsing circuit to provide a clock signal of the multiple clock signals having a clock period that differs from that of others of the multiple clock signals; and
an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits provided to one or more destination circuits, the output management timing circuit including an intermediate clock domain circuit having relaxed input timing constraints and configured to re-clock each of the digital outputs to an intermediate clock frequency.
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Accused Products
Abstract
A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.
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Citations
25 Claims
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1. A circuit comprising:
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a power supply terminal; a clock parsing circuit configured to produce multiple clock signals having different phases; a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal, each digital circuit including an input to receive data and logic to process the data, each digital circuit responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the power supply terminal to process the data to produce a data output; a control circuit coupled to the clock parsing circuit and the plurality of digital circuits, the control circuit to selectively control the clock parsing circuit to provide a clock signal of the multiple clock signals having a clock period that differs from that of others of the multiple clock signals; and an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits provided to one or more destination circuits, the output management timing circuit including an intermediate clock domain circuit having relaxed input timing constraints and configured to re-clock each of the digital outputs to an intermediate clock frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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receiving an input clock signal having a clock period at a clock parsing circuit; generating multiple phase-shifted output clock signals based on the input clock signal using the clock parsing circuit, at least some of the multiple phase-shifted output clock signals having a respective phase offset within an output clock period, at least one of the multiple phase-shifted output clock signals having a clock period that is different from the clock period of the input clock signal; and providing the multiple phase-shifted output clock signals to a plurality of digital circuits to drive the plurality of digital circuits in multiple phases, each digital circuit including a data input to receive data; processing at least a portion of the data at each digital circuit using a unique one of the multiple phase-shifted clock signals to produce a respective data output; managing each of the respective data outputs of each of the plurality of digital circuits provided to one or more destination circuits using an output timing management circuit comprising an intermediate clock domain by re-clocking each of the respective data outputs to the intermediate clock domain using the output timing management circuit monitoring the plurality of digital circuits to detect a transition from an idle state to an on state of at least one of the plurality of digital circuits; dividing the input clock signal to produce an altered output clock signal having an altered output clock period; and providing the altered output clock signal to the clock parsing circuit. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A circuit comprising:
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a clock input configured to receive an input clock signal having an input clock period; multiple digital circuits, each of the multiple digital circuits including an input to receive data and logic to process the data to produce output data; a clock parsing circuit coupled to the clock input and configurable to generate multiple phase-shifted output clock signals based on the input clock signal, at least some of the multiple phase-shifted output clock signals having a respective phase offset within an output clock period, the clock parsing circuit configured to selectively vary a clock period of at least one of the multiple phase-shifted output clock signals to be different from the input clock period, the clock parsing circuit to drive the multiple digital circuits in multiple phases based on at least one of the multiple phase shifted output clock signals and the at least one clock signal to process the data in multiple phases; an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits provided to one or more destination circuits; and a synchronization circuit coupled to each of the multiple digital circuits and configured to receive the input clock signal, the synchronization circuit configurable to synchronize the output data from each of the multiple digital circuits to the input clock signal to produce a synchronized data output. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25)
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Specification