Pulse generation circuit and semiconductor device

• US 9,041,453 B2
• Filed: 03/21/2014
• Issued: 05/26/2015
• Est. Priority Date: 04/04/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Miyake, Hiroyuki, Toyotaka, Kouhei
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): SKIBINSKI, THOMAS S
• Application Number:
  US14/221,523
• Publication Number:
  US 20140300399A1
• Time in Patent Office: 431 Days
• Field of Search: 327/291, 327293-297, 327/241, 327/242, 327/427, 327/434, 327/437, 327/408, 327/165, 327/166, 327170-177, 377/64, 377/68, 377/78, 377/79, 377/54, 345/42, 326/46
• US Class Current: 327/296
• CPC Class Codes: G09G 2300/0404 Matrix technologies
• CPC Class Codes: G09G 2300/0413 Details of dummy pixels or dummy lines in flat panels
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H03K 3/356026 with synchronous operation H03K3/356034, H03K3/356052 take precedence

Abstract

Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.

Claims

1. A pulse generation circuit comprising:

a first unit circuit comprising a first circuit, a second circuit, and a third circuit, the first to third circuits being connected in cascade; and

a second unit circuit comprising a fourth circuit an input of which is connected to the second circuit and an output of which is connected to M (M is an integer of 2 or more) wirings,

wherein the second circuit comprises a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal,

wherein the second circuit is configured to output a first signal from the first output terminal to the first circuit,

wherein the second circuit is configured to output a second signal from the second output terminal to the third circuit,

wherein the second circuit is configured to output a third signal from the third and fourth output terminals to the fourth circuit in accordance with a fourth signal input from the first circuit,

wherein the second circuit is configured to stop the output of the third signal in accordance with a fifth signal input from the third circuit, and

wherein the fourth circuit is configured to generate M pulse signals from the third signal and output the M pulse signals to the M wirings, respectively.

2. The pulse generation circuit according to claim 1,

wherein the second circuit is configured to output a sixth signal to the fourth circuit, and

wherein the fourth circuit is configured to input a constant voltage to the M wirings in accordance with the sixth signal.

3. The pulse generation circuit according to claim 1, wherein the second unit circuit is configured to generate the M pulse signals having pulsed widths corresponding to pulse widths of M control signals.

4. A semiconductor device comprising:

2kMN pixel circuits (k, M, and N are each an integer of 2 or more) which are arranged in an array of 2kM rows and N columns;

N source lines to which the pixel circuits in the same columns are connected and to each of which a source signal is input;

a first gate driver and a second gate driver which each generate a gate signal for selecting the pixel circuit to which the source signal is input; and

2kM gate lines to which the pixel circuits in the same rows are connected and to each of which the gate signal is input,

wherein the first gate driver and the second gate driver each comprise the pulse generation circuit according to claim 1.

5. A pulse generation circuit, which includes a single conductivity type transistor, comprising:

k (k is an integer of 2 or more)-stage first unit circuits connected in cascade; and

k second unit circuits in each of which an input is connected to one of the first unit circuits and an output is connected to M (M is an integer of 2 or more) first wirings,

the first unit circuit comprising;

a second wiring to which a first voltage is input;

a third wiring to which a second voltage lower than the first voltage is input;

a first node, a second node, a third node, and a fourth node;

a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal outputting voltage changes in the first node, the second node, the third node, and the fourth node as a first signal, a second signal, a third signal, and a fourth signal, respectively;

a first input terminal and a second input terminal to which a first control signal and a second control signal are input, respectively;

a third input terminal to which a third signal generated in the first unit circuit in a previous stage is input;

a fourth input terminal to which a fourth signal generated in the first unit circuit in a next stage is input;

a first transistor which connects the first node and the second wiring and a gate of which is connected to the third input terminal;

a second transistor which connects the first node and the third wiring and a gate of which is connected to the second node;

a third transistor which connects the second node and the second wiring and a gate of which is connected to the fourth input terminal;

a fourth transistor which connects the second node and the third wiring and a gate of which is connected to the third input terminal;

a fifth transistor which connects the fourth node and the first input terminal and a gate of which is connected to the first node;

a sixth transistor which connects the fourth node and the third wiring and a gate of which is connected to the second node;

a seventh transistor which connects the third node and the second input terminal and a gate of which is connected to the first node; and

an eighth transistor which connects the third node and the third wiring and a gate of which is connected to the second node,

the second unit circuits each comprising M third unit circuits to which different M control signals are input, and

the third unit circuit comprising;

the third wiring to which the second voltage is input;

a fifth input terminal to which the first signal is input from the first unit circuit;

a sixth input terminal to which the second signal is input from the first unit circuit;

a seventh input terminal to which any one of the M control signals is input;

a fifth output terminal to which any one of the M first wirings is connected;

a ninth transistor which connects the fifth output terminal and the fifth input terminal and a gate of which is connected to the fifth input terminal; and

a tenth transistor which connects the fifth output terminal and the third wiring and a gate of which is connected to the sixth input terminal.

6. The pulse generation circuit according to claim 5, wherein the first unit circuit includes an eleventh transistor in which the first voltage is input to a gate thereof and which connects the first node and the gate of the fifth transistor.

7. The pulse generation circuit according to claim 5, wherein the first unit circuit includes a twelfth transistor in which the first voltage is input to a gate thereof and which connects the first node and the gate of the seventh transistor.

8. The pulse generation circuit according to claim 5,

the first unit circuit comprising:

a ninth input terminal to which a third control signal is input; and

a thirteenth transistor which connects the second node and the second wiring and a gate of which is connected to the ninth input terminal.

9. The pulse generation circuit according to claim 5,

the first unit circuit comprising:

a tenth input terminal to which a fourth control signal is input; and

a fourteenth transistor which connects the second node and the second wiring and a gate of which is connected to the tenth input terminal.

10. The pulse generation circuit according to claim 5, wherein the third unit circuit includes a fifteenth transistor in which the first voltage is input to a gate thereof and connects the seventh input terminal and the gate of the ninth transistor.

11. A semiconductor device comprising:

2kMN pixel circuits (k, M, and N are each an integer of 2 or more) which are arranged in an array of 2kM rows and N columns;

N source lines to which the pixel circuits in the same columns are connected and to each of which a source signal is input;

a first gate driver and a second gate driver which each generate a gate signal for selecting the pixel circuit to which the source signal is input; and

2kM gate lines to which the pixel circuits in the same rows are connected and to each of which the gate signal is input,

wherein the first gate driver and the second gate driver each comprise the pulse generation circuit according to claim 5.

12. A semiconductor device comprising:

2kMN pixel circuits (k, M, and N are each an integer of 2 or more) which are arranged in an array of 2kM rows and N columns;

N source lines to which the pixel circuits in the same columns are connected and to each of which a source signal is input;

a first gate driver and a second gate driver which each generate a gate signal for selecting the pixel circuit to which the source signal is input; and

2kM gate lines to which the pixel circuits in the same rows are connected and to each of which the gate signal is input,

wherein the 2kM gate lines are alternately connected to the first gate driver and the second gate driver in every M rows,

the first gate driver and the second gate driver each comprising;

a single conductivity type transistor;

a shift register including k-stage first unit circuits connected in cascade; and

k second unit circuits in each of which an input is connected to one of the first unit circuits and an output is connected to M wirings,

wherein one of the first unit circuits comprises a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal,

wherein the one of the first unit circuits is configured to output a first signal from the first output terminal to a previous stage of the one of the first unit circuits,

wherein the one of the first unit circuits is configured to output a second signal from the second output terminal to a next stage of the one of the first unit circuits,

wherein the one of the first unit circuits is configured to output a third signal from the third and fourth output terminals to one of the second unit circuits in accordance with a fourth signal input from the previous stage of the one of the first unit circuits,

wherein each of the second unit circuits has a function of dividing an output signal from each of the first unit circuits into M signals in accordance with M control signals and outputting the M signals to the M wirings as the gate signals.

13. The semiconductor device according to claim 12, wherein each of the second unit circuits is configured to generate the M gate signals having pulsed widths corresponding to pulse widths of the M control signals.