System and method for improving error distribution in multi-level memory cells

• US 9,042,168 B1
• Filed: 04/14/2014
• Issued: 05/26/2015
• Est. Priority Date: 03/10/2008
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Yang, Xueshi
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US14/252,303
• Time in Patent Office: 407 Days
• Field of Search: 365/185.03, 365/185.18, 365/185.04, 365/185.09, 365/185.12, 365/185.17, 365/185.23, 365/189.011, 365/189.14, 365/230.04, 365/230.06
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A system including a state set module to arrange states of a memory cell in three sets. The memory cell stores three bits when programmed to a state. Each set includes three rows of bits. In a set, a row includes one of the three bits of the states. The first, second, and third rows of the first, second, and third sets include a first number of state transitions. The second, third, and first rows of the first, second, and third sets include a second number of state transitions. The third, first, and second rows of the first, second, and third sets include a third number of state transitions. A write module writes first, second, and third portions of data to a plurality of memory cells, each memory cell storing the three bits when programmed to a state, using states selected respectively from the first, second, and third sets.

Claims

1. A system comprising:

a state set module configured to

arrange a plurality of states of a memory cell in (i) a first state set, (ii) a second state set, and (iii) a third state set,

wherein the memory cell is configured to store (i) a first bit, (ii) a second bit, and (iii) a third bit in response to being programmed to one of the plurality of states,

wherein each of the first state set, the second state set, and the third state set includes (i) a first row of bits including the first bits of the plurality of states, (ii) a second row of bits including the second bits of the plurality of states, and (iii) a third row of bits including the third bits of the plurality of states,

wherein the first row of bits of the first state set (i) is identical to the second row of bits of the second state set and the third row of bits of the third state set and (ii) includes a first number of state transitions,

wherein the second row of bits of the first state set (i) is identical to the third row of bits of the second state set and the first row of bits of the third state set and (ii) includes a second number of state transitions,

wherein the third row of bits of the first state set (i) is identical to the first row of bits of the second state set and the second row of bits of the third state set and (ii) includes a third number of state transitions; and

a write module configured to

receive data for writing to a plurality of memory cells, wherein each memory cell of plurality of memory cells is configured to store (i) the first bit, (ii) the second bit, and (iii) the third bit in response to being programmed to one of the plurality of states,

write a first portion of the data to the plurality of memory cells using states from the first state set,

write a second portion of the data to the plurality of memory cells using states from the second state set, and

write a third portion of the data to the plurality of memory cells using states from the third state set.

2. The system of claim 1, wherein the first number of state transitions is different from the second number of state transitions, and wherein the second number of state transitions is different from the third number of state transitions.

3. The system of claim 1, wherein in each of the first state set, the second state set, and the third state set, each of the plurality of states differs from an adjacent one of the plurality of states by one bit.

4. The system of claim 1, wherein:

a sum of a number of transitions in the first rows of the first state set, the second state set, and the third state set is equal to a sum of a number of transitions in the second rows of the first state set, the second state set, and the third state set; and

the sum of the number of transitions in the second rows of the first state set, the second state set, and the third state set is equal to a sum of a number of transitions in the third rows of the first state set, the second state set, and the third state set.

5. The system of claim 1, wherein:

the first bits, the second bits, and the third bits of the plurality of memory cells are respectively arranged along a first page, a second page, and a third page; and

an error distribution in the first page, the second page, and the third page is even.

6. The system of claim 1, further comprising an error correcting code module configured to generate the data based on an error-correcting code.

7. The system of claim 1, further comprising:

a memory map module configured to store a pattern used to select states from the first state set, the second state set, and the third state set for writing the data to the plurality memory cells; and

a read module configured to read the data from the plurality of memory cells in accordance with the pattern.

8. The system of claim 1, wherein the plurality of memory cells includes NAND flash memory cells or NOR flash memory cells.

9. A flash memory comprising the system of claim 1.

10. The flash memory of claim 9, wherein the flash memory comprises a NAND flash memory or a NOR flash memory.

11. A method comprising:

arranging a plurality of states of a memory cell in (i) a first state set, (ii) a second state set, and (iii) a third state set,

wherein the memory cell is configured to store (i) a first bit, (ii) a second bit, and (iii) a third bit in response to being programmed to one of the plurality of states,

wherein each of the first state set, the second state set, and the third state set includes (i) a first row of bits including the first bits of the plurality of states, (ii) a second row of bits including the second bits of the plurality of states, and (iii) a third row of bits including the third bits of the plurality of states,

wherein the first row of bits of the first state set (i) is identical to the second row of bits of the second state set and the third row of bits of the third state set and (ii) includes a first number of state transitions,

wherein the second row of bits of the first state set (i) is identical to the third row of bits of the second state set and the first row of bits of the third state set and (ii) includes a second number of state transitions,

wherein the third row of bits of the first state set (i) is identical to the first row of bits of the second state set and the second row of bits of the third state set and (ii) includes a third number of state transitions;

receiving data for writing to a plurality of memory cells, wherein each memory cell of plurality of memory cells is configured to store (i) the first bit, (ii) the second bit, and (iii) the third bit in response to being programmed to one of the plurality of states;

writing a first portion of the data to the plurality of memory cells using states from the first state set;

writing a second portion of the data to the plurality of memory cells using states from the second state set; and

writing a third portion of the data to the plurality of memory cells using states from the third state set.

12. The method of claim 11, wherein the first number of state transitions is different from the second number of state transitions, and wherein the second number of state transitions is different from the third number of state transitions.

13. The method of claim 11, wherein in each of the first state set, the second state set, and the third state set, each of the plurality of states differs from an adjacent one of the plurality of states by one bit.

14. The method of claim 11, wherein:

a sum of a number of transitions in the first rows of the first state set, the second state set, and the third state set is equal to a sum of a number of transitions in the second rows of the first state set, the second state set, and the third state set; and

the sum of the number of transitions in the second rows of the first state set, the second state set, and the third state set is equal to a sum of a number of transitions in the third rows of the first state set, the second state set, and the third state set.

15. The method of claim 11, wherein:

the first bits, the second bits, and the third bits of the plurality of memory cells are respectively arranged along a first page, a second page, and a third page; and

an error distribution in the first page, the second page, and the third page is even.

16. The method of claim 11, further comprising generating the data based on an error-correcting code.

17. The method of claim 11, further comprising:

storing a pattern used to select states from the first state set, the second state set, and the third state set for writing the data to the plurality memory cells; and

reading the data from the plurality of memory cells in accordance with the pattern.

18. The method of claim 11, wherein the plurality of memory cells includes NAND flash memory cells or NOR flash memory cells.