Self-repairing memory

• US 9,042,191 B2
• Filed: 03/15/2013
• Issued: 05/26/2015
• Est. Priority Date: 08/12/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: O'Connell, Cormac Michael
• Primary Examiner(s): Yang, Han
• Application Number:
  US13/840,386
• Publication Number:
  US 20130212449A1
• Time in Patent Office: 802 Days
• Field of Search: 365/200, 365/201, 365/235, 365/185.09
• US Class Current: 365/200
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G11C 29/18 Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/4401 for self repair

Abstract

A memory array has a plurality of rows including a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each first bit indicates whether the associated memory word has had an error. Each redundancy row of a plurality of redundancy rows includes a plurality of redundancy words. Each redundancy word is associated with a memory word. A corrected data cache has at least one repair word configured to store corrected data and at least one status bit associated with the at least one repair word, the status bit indicating whether the corrected data stored in the repair word is a pending repair. The corrected data cache is configured to write the corrected data stored in the repair word to at least one of a counterpart memory word or a counterpart redundancy word.

Claims

1. A memory comprising:

a memory array having a plurality of rows, each row of the plurality of rows of the memory array including a plurality of memory words;

a plurality of first bits, each first bit of the plurality of first bits associated with a memory word of the plurality of memory words of the each row of the plurality of rows of the memory array, wherein a logic state of the each first bit indicates whether the memory word associated with the each first bit has had a failed bit;

a plurality of redundancy rows, each redundancy row of the plurality of redundancy rows including a plurality of redundancy words, each redundancy word of the plurality of redundancy words associated with a corresponding memory word of the plurality of memory words of the each row of the plurality of rows of the memory array; and

a corrected data cache having at least one repair word configured to store corrected data and at least one status bit associated with the at least one repair word, the status bit indicating whether the corrected data stored in the repair word is a pending repair, the corrected data cache configured to write the corrected data stored in the repair word to at least one of a counterpart memory word or a counterpart redundancy word.

2. The memory of claim 1, further comprising:

a self-repair address comparator configured to compare an address associated with the corrected data and an address to be accessed.

3. The memory of claim 1, further comprising a cache stack counter configured to monitor a number of pending repairs in the corrected data cache.

4. The memory of claim 1, wherein the corrected data cache is configured to have a maximum number of pending repairs ranging from 1 to 4 per mega-byte (MB) of memory array.

5. The memory of claim 1, further comprising:

a word logic engine configured to process each memory word of the plurality of memory words of a row of the memory array; and

a bit-tag logic engine configured to process the each first bit associated with the each memory word of the plurality of memory words to be processed.

6. The memory of claim 1, further comprising an error correct engine configured

to cause a change in the state of the each first bit based on an error in the memory word associated with the each first bit and write the memory word with the changed bit into the corrected data cache as the corrected data;

and/or

to cause a change in the state of the each second bit based on an error in the redundancy word associated with the each second bit and write the redundancy word with the changed bit into the corrected data cache as the corrected data.

7. The memory of claim 1, further comprising an error correction engine configured

to generate an error-repair flag based on the state of the each first bit and an error in the memory word associated with the each first bit;

and/or

to generate the error-repair flag based on the state of the each second bit and an error in the redundancy word associated with the each second bit.

8. A computing device comprising:

a processor; and

a memory macro connected to the processor comprising;

a memory array having a plurality of rows, each row of the plurality of rows of the memory array including a plurality of memory words;

a plurality of first bits, each first bit of the plurality of first bits associated with a memory word of the plurality of memory words of the each row of the plurality of rows of the memory array, wherein a logic state of the each first bit indicates whether the memory word associated with the each first bit has had a failed bit;

a plurality of redundancy rows, each redundancy row of the plurality of redundancy rows including a plurality of redundancy words, each redundancy word of the plurality of redundancy words associated with a corresponding memory word of the plurality of memory words of the each row of the plurality of rows of the memory array; and

a corrected data cache having at least one repair word configured to store corrected data and at least one status bit associated with the at least one repair word, the status bit indicating whether the corrected data stored in the repair word is a pending repair, the corrected data cache configured to write the corrected data stored in the repair word to at least one of a counterpart memory word or a counterpart redundancy word.

9. The computing device of claim 8, further comprising:

a self-repair address comparator configured to compare an address associated with the corrected data and an address to be accessed.

10. The computing device of claim 8, further comprising a cache stack counter configured to monitor a number of pending repairs in the corrected data cache.

11. The computing device of claim 8, wherein the corrected data cache is configured to have a maximum number of pending repairs ranging from 1 to 4 per mega-byte (MB) of memory array.

12. The computing device of claim 8, further comprising:

a word logic engine configured to process each memory word of the plurality of memory words of a row of the memory array; and

a bit-tag logic engine configured to process the each first bit associated with the each memory word of the plurality of memory words to be processed.

13. The computing device of claim 8, further comprising an error correct engine configured

to cause a change in the state of the each first bit based on an error in the memory word associated with the each first bit and write the memory word with the changed bit into the corrected data cache as the corrected data;

and/or

to cause a change in the state of the each second bit based on an error in the redundancy word associated with the each second bit and write the redundancy word with the changed bit into the corrected data cache as the corrected data.

14. The computing device of claim 8, further comprising an error correction engine configured

to generate an error-repair flag based on the state of the each first bit and an error in the memory word associated with the each first bit;

and/or

to generate the error-repair flag based on the state of the each second bit and an error in the redundancy word associated with the each second bit.

15. A method of operating a memory, the method comprising:

detecting an error which occurs during accessing an address in a memory array;

correcting data corresponding with the detected error;

storing the corrected data in a corrected data cache;

associating the corrected data with the address in the memory array;

outputting the corrected data to circuitry external to the memory;

determining whether the error is a hard error or a soft error; and

writing the corrected data stored in the corrected data cache back into the memory array if the error is a soft error.

16. The method of claim 15, further comprising:

checking a capacity status of the corrected data cache after storing the corrected data in the corrected data cache; and

outputting a signal when a number of corrected data stored in the corrected data cache exceeds a threshold value.

17. The method of claim 15, further comprising:

if the error is a hard error, writing the corrected data back into a redundancy memory; and

associating the address in the memory array with an address of the corrected data in the redundancy memory.

18. The method of claim 15, further comprising:

if the error is a hard error, permanently storing the corrected data in the corrected data cache; and

directing a subsequent access of the address to the corrected data stored in the corrected data cache.

19. The method of claim 15, wherein writing the data back into the memory array comprises performing a hidden write operation.

20. The method of claim 15, wherein writing the data back into the memory array comprises writing back into the memory array during a cycle when the memory array is not accessed by external circuitry.