Apparatus and methods for tuning a voltage controlled oscillator
First Claim
1. An auto-tuning circuit for tuning a voltage controlled oscillator (VCO) during a coarse tuning mode, the auto-tuning circuit comprising:
- a prescaler circuit configured to receive a VCO clock signal from the VCO and to generate a divided clock signal, the prescaler circuit having a selectable division ratio;
a counter module including a first counter and a second counter, the first counter configured to operate with the second counter to control a value of the selectable division ratio of the prescaler circuit, the counter module configured to receive a division control signal M and the divided clock signal, and to generate a phase-frequency detector (PFD) feedback signal based on the division control signal M and the divided clock signal; and
a digital processing logic circuit configured to receive the divided clock signal, the digital processing logic circuit including a cycle counter configured to count a number of cycles of the divided clock signal generated by the prescaler circuit that occur during a calibration interval, the digital processing logic circuit further configured to set a value of a capacitor array control signal based on the number of cycles counted.
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Abstract
Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.
16 Citations
20 Claims
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1. An auto-tuning circuit for tuning a voltage controlled oscillator (VCO) during a coarse tuning mode, the auto-tuning circuit comprising:
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a prescaler circuit configured to receive a VCO clock signal from the VCO and to generate a divided clock signal, the prescaler circuit having a selectable division ratio; a counter module including a first counter and a second counter, the first counter configured to operate with the second counter to control a value of the selectable division ratio of the prescaler circuit, the counter module configured to receive a division control signal M and the divided clock signal, and to generate a phase-frequency detector (PFD) feedback signal based on the division control signal M and the divided clock signal; and a digital processing logic circuit configured to receive the divided clock signal, the digital processing logic circuit including a cycle counter configured to count a number of cycles of the divided clock signal generated by the prescaler circuit that occur during a calibration interval, the digital processing logic circuit further configured to set a value of a capacitor array control signal based on the number of cycles counted. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A phase-locked loop comprising:
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a capacitor array including a plurality capacitors digitally selectable by a capacitor array control signal; a voltage controlled oscillator (VCO) having a voltage input and configured to generate a VCO clock signal, a frequency of the VCO clock signal based on a voltage level at the voltage input and on a value of the capacitor array control signal; a prescaler circuit configured to receive the VCO clock signal and to generate a divided clock signal, the prescaler circuit having a selectable division ratio; a counter module including a first counter and a second counter, the first counter configured to operate with the second counter to control the selectable division ratio of the prescaler circuit, the counter module configured to receive a division control signal M and the divided clock signal, and to generate a phase-frequency detector (PFD) feedback signal based on the division control signal M and the divided clock signal; and a digital processing logic circuit configured to receive the divided clock signal, the digital processing logic circuit including a cycle counter configured to count a number of cycles of the divided clock signal generated by the prescaler circuit that occur during a calibration interval, the digital processing logic circuit further configured to set the value of the capacitor array control signal based on the number of cycles counted. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A method of auto-tuning in a phase-locked loop (PLL), the method comprising:
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generating a voltage controlled oscillator (VCO) clock signal using a VCO coupled to a capacitor array, a frequency of the VCO clock signal based on an input voltage of the VCO and on a value of a capacitor array control signal of the capacitor array; dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio; controlling a value of the selectable division ratio using a first counter and a second counter of a counter module; generating a phase-frequency detector (PFD) feedback signal based on a division control signal M and the divided clock signal using the counter module; counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit; and determining the value of the capacitor array control signal based on the number of cycles counted during the calibration interval. - View Dependent Claims (19, 20)
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Specification