Host controller

• US 9,043,506 B2
• Filed: 10/16/2013
• Issued: 05/26/2015
• Est. Priority Date: 01/26/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Feeley, Peter, Leibowitz, Robert N., Radke, William H., Galbo, Neal A., Tsai, Victor Y.
• Primary Examiner(s): Sun, Michael
• Application Number:
  US14/055,436
• Publication Number:
  US 20140108678A1
• Time in Patent Office: 587 Days
• Field of Search: None
• US Class Current: 710/24
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Claims

1. An apparatus, comprising:

a number of memory devices; and

a host controller coupled to the number of memory devices;

wherein the host controller is configured to locate a number of commands stored in memory associated with a host system using a pointer that is stored in a register in the host controller,

wherein the host controller transmits the number of commands to the number of memory devices, wherein the number of commands are based on device class dependent information stored in the memory associated with the host system; and

wherein the number of memory devices execute the number of commands with a memory device controller on the number of memory devices.

2. The apparatus of claim 1, wherein device class dependent information is stored in the memory associated with the host system.

3. The apparatus of claim 1, wherein the pointer directs the host controller to the number of commands and to device class dependent information stored in the memory associated with the host system.

4. The apparatus of claim 1, wherein the number of commands are based on device class dependent information and built by a host processor in the memory associated with the host system.

5. The apparatus of claim 1, wherein the number of commands are built in the memory associated with the host system.

6. The apparatus of claim 1, wherein the number of commands are built by a host processor coupled to the host controller.

7. The apparatus of claim 1, wherein the number of memory devices are external to the host controller.

8. The apparatus of claim 1, wherein the number of memory devices execute the number of commands with the memory device controller on the number of memory devices to read data from the number of memory devices.

9. The apparatus of claim 1, wherein the number of memory devices execute the number of commands with the memory device controller on the number of memory devices to write data to the number of memory device.

10. The apparatus of claim 1, wherein the memory associated with the host system is host system memory and/or host controller memory.

11. An apparatus, comprising:

a host controller configured to;

locate a command stored in memory associated with a host system using a pointer from a register in the host controller; and

direct access of a memory device to the command by transferring the command to the memory device for execution by the memory device, wherein execution includes initiating a direct memory access (DMA) read of write command data in the memory associated with the host system, locating device class dependent information in the memory using the pointer, and returning the write command data to the memory device.

12. The apparatus of claim 11, wherein the command is built by a host processor in the memory associated with the host system.

13. The apparatus of claim 11, wherein the memory device is external to the host system.

14. The apparatus of claim 11, wherein the memory device executes the command by reading data from and/or writing data to the memory device.

15. An apparatus, comprising:

a host controller coupled to a number of memory devices external to a host system and to a host processor on the host system;

wherein the host controller is configured to locate a number of commands and device class dependent information that is stored in memory associated with the host system using a pointer stored in a register in the host controller that directs the host controller to the commands,

wherein the host controller transmits the number of commands, which are based on device class dependent information and are built by the host processor in the memory associated with the host system, to the number of memory devices external to the host controller, and

wherein the number of memory devices execute the number of commands with a memory device controller on the number of memory devices by initiating a direct memory access (DMA) transfer of read command data from the number of memory devices to the memory associated with the host system and writing the read command data to the memory associated with the host system.

16. The apparatus of claim 15, wherein the memory associated with the host system is host system memory and/or host controller memory.

17. The apparatus of claim 15, wherein device class dependent information is information that indicates operating parameters that are specific to one or more of the number of the memory devices.

18. The apparatus of claim 15, wherein the host processor runs a device driver to store device class independent information in the memory associated with the host system.

19. The apparatus of claim 15, wherein device class independent information is information that indicates operating parameters for memory devices independent of the device type.

20. The apparatus of claim 15, wherein device class independent information is stored in one or more registers in the memory associated with the host system.