High speed input/output performance in solid state devices

• US 9,043,531 B2
• Filed: 06/25/2009
• Issued: 05/26/2015
• Est. Priority Date: 06/25/2008
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: Calvert, William, Boorman, Stephen Russell, Haynes, Simon Mark
• Primary Examiner(s): THAI, TUAN V
• Application Number:
  US12/492,109
• Publication Number:
  US 20120239852A1
• Time in Patent Office: 2,161 Days
• Field of Search: 711/103
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A method of transferring data in a flash storage device comprising a random access memory and a plurality of channels of a flash array is provided. The method comprises receiving a plurality of data segments from a host system, storing the plurality of data segments in the random access memory, allocating the plurality of data segments among the plurality of channels of the flash array, and writing the allocated data segments from the random access memory to the respective channels of the flash array.

Claims

1. A method of storing data in a flash storage device, the method comprising:

receiving a plurality of data sectors from a host system, wherein each of the data sectors is associated with a host logical address;

storing a plurality of data segments in the random access memory, wherein each data segment comprises one of the plurality of data sectors from the host system;

mapping the host logical address of each of the plurality of data sectors to a flash logical address of a corresponding data segment, wherein the mapping to the flash logical address is based on the respective host logical address;

calculating a channel assignment for each of the plurality of data segments based on the flash logical address of the respective data segment;

allocating the plurality of data segments among a plurality of channels of a flash array based on the channel assignment for each of the plurality of data segments;

generating a plurality of write commands for the plurality of allocated data segments;

providing each of the plurality of write commands to a respective queue associated with a channel to which the write command is allocated; and

for each queue storing write commands, sequentially sending the queued write commands to one or more flash memories via the channel to which the write commands are allocated, and sequentially providing a respective data segment in connection with sending each queued write command from the random access memory via the memory channel corresponding to the queue.

2. The method of claim 1, wherein the data segments allocated to a respective one of the channels of the flash array are written sequentially to the respective one of the channels of the flash array.

3. The method of claim 1, wherein the allocated data segments are written to the respective channels of the flash array in parallel.

4. The method of claim 1, wherein the allocated data segments are written from the random access memory to the respective channels of the flash array at a predetermined time interval.

5. The method of claim 1, wherein the allocated data segments are written from the random access memory to the respective channels of the flash array after a predetermined number of data segments have been received and allocated to at least one of the plurality of channels of the flash array.

6. The method of claim 5, wherein the predetermined number of data segments comprises one block of data.

7. The method of claim 1, wherein each of the plurality of data segments comprises more than one of the plurality of data sectors.

8. A flash storage device comprising:

a random access memory;

a flash array comprising a plurality of flash memories and a respective plurality of channels; and

a controller configured to;

receive a plurality of data sectors from a host system, wherein each of the data sectors is associated with a host logical address;

store a plurality of data segments in the random access memory, wherein each data segment comprises one of the plurality of data sectors from the host system;

map the host logical address of each of the plurality of data sectors to a flash logical address of a corresponding data segment, wherein the mapping to the flash logical address is based on the respective host logical address;

calculate a channel assignment for each of the plurality of data segments based on the flash logical address of the respective data segment;

allocate the plurality of data segments among the plurality of channels of the flash array based on the channel assignment for each of the plurality of data segments;

generate a plurality of write commands for the plurality of allocated data segments;

provide each of the plurality of write commands to a respective queue associated with a channel to which the write command is allocated; and

for each queue storing write commands, sequentially send the queued write commands to one or more flash memories via respective channels to which the write commands are allocated, and provide a respective data segment in connection with sending each queued write command from the random access memory via the memory channel corresponding to the queue.

9. The flash storage device of claim 8, wherein the controller is configured to sequentially write data segments allocated to a respective one of the channels of the flash array to the respective one of the channels of the flash array.

10. The flash storage device of claim 8, wherein the controller is configured to write the allocated data segments to the respective channels of the flash array in parallel.

11. The flash storage device of claim 8, wherein the controller is configured to write the allocated data segments from the random access memory to the respective channels of the flash array at a predetermined time interval.

12. The flash storage device of claim 8, wherein the controller is configured to write the allocated data segments from the random access memory to the respective channels of the flash array after a predetermined number of data segments have been received and allocated to at least one of the plurality of channels of the flash array.

13. The flash storage device of claim 12, wherein the predetermined number of data segments comprises one block of data.

14. The flash storage device of claim 8, wherein each of the plurality of data segments comprises more than one of the plurality of data sectors.