Distributed ECC engine for storage media

• US 9,043,669 B1
• Filed: 05/18/2012
• Issued: 05/26/2015
• Est. Priority Date: 05/18/2012
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Mateo, Noeme P., Climaco, Joey B., Bruce, Rey H.
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US13/475,878
• Time in Patent Office: 1,103 Days
• Field of Search: 714/767, 714/769, 714/770, 714/772, 714/773, 714/757, 714/747, 714/751, 714/763, 714/764, 714/766, 714/799, 714/800, 714/801, 714/820, 714/701, 714/6.2, 714/6.21, 714/6.23, 714/6.24, 714/54, 714/52, 714/42, 365/200, 365/201, 711/111, 711/112
• US Class Current: 714/757
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: H03M 13/27 using interleaving techniques

Abstract

Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts; the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices; and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.

Claims

1. An apparatus for handling distributed error correction code (ECC) operations, the apparatus comprising:

a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts that are partitioned from a contiguous data;

the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices;

the plurality of ECC engines configured to use respective computed ECC parts corresponding to respective ones of the multiple data parts;

wherein the plurality of ECC engines comprises a first ECC engine and a second ECC engine;

wherein the storage media devices comprises;

a first group comprising a first plurality of storage media devices and a second group comprising a second plurality of storage media devices;

a first storage interface controller coupled to the first ECC engine and to the first group;

wherein the first storage interface is coupled between the first ECC engine and the first group;

wherein the first storage interface comprises first logic to provide access to and directly control each of the first plurality of storage devices in the first group and to provide a first path between the first plurality of storage devices and the first ECC engine for the first data part and first computed ECC part; and

a second storage interface controller coupled to the second ECC engine and to the second group;

wherein the second storage interface is coupled between the second ECC engine and the second group;

wherein the second storage interface comprises second logic to provide access to and directly control each of the second plurality of storage devices in the second group and to provide a second path between the second plurality of storage devices and the second ECC engine for the second data part and second computed ECC part;

a processor configured to partition the contiguous data into the multiple data parts;

wherein the multiple data parts comprises a first data part and a second data part;

wherein, in parallel, the first ECC engine performs an ECC operation on the first data part including computing a first computed ECC part and the second ECC engine performs another ECC operation on the second data part including computing a second computed ECC part; and

a storage direct memory access (DMA) controller coupled to the processor and to the first and second storage interface controllers;

wherein the storage DMA controller is configured to write or read the first data part and the first computed ECC part in a first storage media device in the first group;

wherein the storage DMA controller is configured to write or read the second data part and the second computed ECC part in another storage media device in the second group.

2. The apparatus of claim 1, wherein the ECC engines are included in the storage DMA (direct memory access) controller.

3. The apparatus of claim 2, wherein the storage DMA controller includes a DMA &

ECC instruction buffer configured to store DMA instructions for use in DMA operations and ECC configurations for use in ECC operations.

4. The apparatus of claim 2, wherein the storage DMA controller includes a data path &

ECC configuration control block configured to permit DMA operations with distributed ECC.

5. The apparatus of claim 1, wherein the ECC engines are used with a storage system.

6. The apparatus of claim 5, wherein the storage system includes a local memory system.

7. The apparatus of claim 5, wherein the storage system includes a host system interface configured to receive requests from a host system.

8. The apparatus of claim 5, wherein the storage system includes a local memory system configured to store the multiple data parts that are read from the storage media devices.

9. The apparatus of claim 5, wherein the storage system includes a local memory system configured to store the multiple data parts that are to be written to the storage media devices.

10. The apparatus of claim 1, wherein the multiple data parts are written to different locations in the storage media devices.

11. The apparatus of claim 10, wherein the different locations comprises different groups in the storage media devices.

12. The apparatus of claim 1, wherein the multiple data parts are read from different locations in the storage media devices.

13. The apparatus of claim 12, wherein the different locations comprises different groups in the storage media devices.

14. The apparatus of claim 1, wherein the plurality of ECC engines has a respective ECC engine that performs an ECC operation on a respective data part in the multiple data parts.

15. The apparatus of claim 1, wherein an ECC operation comprises an ECC encode operation.

16. The apparatus of claim 1, wherein an ECC operation comprises an ECC detect operation.

17. The apparatus of claim 1, wherein an ECC operation comprises an ECC correct operation.

18. The apparatus of claim 1, wherein the storage media devices are coupled to the storage interface controllers.

19. The apparatus of claim 18, wherein the ECC engines are included in the storage interface controllers.

20. The apparatus of claim 1, wherein the ECC engines comprise a plurality of ECC encode and detect modules and a plurality of ECC correct modules, wherein a given subset of the plurality of ECC encode and detect modules is coupled to and is sharing a given ECC correct module of the plurality of ECC correct modules.

21. The apparatus of claim 20, wherein the ECC engines are included in the storage DMA controller.

22. The apparatus of claim 20, wherein the plurality of ECC encode and detect modules are included in the storage interface controllers and the plurality of ECC correct modules are included in the storage DMA controller.

23. The apparatus of claim 1, wherein the ECC engines are included in the storage interface controllers.

24. The apparatus of claim 1, wherein an ECC engine will compute a respective computed ECC part for a respective data part.

25. The apparatus of claim 1, wherein a number of storage interface controllers coupled to the storage media devices and a number of storage DMA controllers can be configured to achieve at least one of an improved performance, decrease size, and decreased cost.

26. The apparatus of claim 1, wherein the storage media devices comprise non-volatile memory devices.

27. The apparatus of claim 1, wherein the first storage interface controller is in a first chip and the second storage interface controller is in a second chip.

28. A method for handling distributed error correction code (ECC) operations, the method comprising:

partitioning a contiguous data into multiple data parts;

wherein the multiple data parts comprises a first data part and a second data part;

performing ECC operations in parallel on the multiple data parts, comprising;

in parallel, performing an ECC operation on a first data part including computing a first computed ECC part and performing another ECC operation on a second data part including computing a second computed ECC part; and

the performing ECC operations including using respective computed ECC parts corresponding to respective ones of the multiple data parts;

writing or reading the first data part and the first computed ECC part in a first storage media device in a first group comprising a first plurality of storage media devices;

writing or reading the second data part and the second computed ECC part in another storage media device in a second group in a second plurality of storage media devices;

wherein a first storage interface comprises first logic provide a first path between the first storage media and the first ECC engine for the first data part and first computed ECC part;

wherein a second storage interface comprises second logic to provide a second path between the second storage media and the second ECC engine for the second data part and second computed ECC part.

29. The method of claim 28, wherein the ECC operations is performed in a storage DMA (direct memory access) controller.

30. The method of claim 28, further comprising:

storing DMA instructions for use in DMA operations and ECC configurations for use in ECC operations.

31. The method of claim 28, wherein the ECC operation is used with a storage system.

32. The method of claim 28, further comprising:

storing the multiple data parts that are read from the storage media devices.

33. The method of claim 28, further comprising:

storing the multiple data parts that are to be written to the storage media devices.

34. The method of claim 28, wherein the multiple data parts are written to different locations in the storage media devices.

35. The method of claim 34, wherein the different locations comprises different groups in the storage media devices.

36. The method of claim 28, wherein the multiple data parts are read from different locations in the storage media devices.

37. The method of claim 36, wherein the different locations comprises different groups in the storage media devices.

38. The method of claim 28, wherein the multiple data parts comprises partitions in the contiguous data.

39. The method of claim 28, further comprising:

performing an ECC operation on a respective data part in the multiple data parts.

40. The method of claim 28, wherein an ECC operation comprises an ECC encode operation.

41. The method of claim 28, wherein an ECC operation comprises an ECC detect operation.

42. The method of claim 28, wherein an ECC operation comprises an ECC correct operation.

43. The method of claim 28, wherein the ECC operations are performed a plurality of storage interface controllers.

44. The method of claim 28 wherein the ECC operations are performed in a storage DMA controller.

45. The method of claim 28 wherein the ECC operations comprises at least one of ECC error encode, ECC error detect, and ECC error correct;

and

wherein the ECC error encode and ECC error detect are performed in a plurality of storage interface controllers and the ECC error correct is performed in a storage DMA controller.

46. The method of claim 28, wherein the storage media devices are coupled to a number of storage interface controllers which are coupled to a number of storage DMA controllers, and wherein the number of storage interface controllers and the number of storage DMA controllers can be configured to achieve at least one of an improved performance, decrease size, and decreased cost.

47. The method of claim 28, wherein the storage media devices comprise non-volatile memory devices.

48. The method of claim 28, wherein the ECC operations are performed in a first storage interface controller in a first chip and in a second storage interface controller in a second chip.

49. An article of manufacture, comprising:

a non-transitory computer-readable medium having stored thereon instructions to;

partitioning a contiguous data into multiple data parts;

wherein the multiple data parts comprises a first data part and a second data part;

perform ECC operations in parallel on the multiple data parts, comprising;

in parallel, performing an ECC operation on a first data part including computing a first computed ECC part and performing another ECC operation on a second data part including computing a second computed ECC part; and

the performing ECC operations including use of respective computed ECC parts corresponding to respective ones of the multiple data parts;

write or read the first data part and the first computed ECC part in a first storage media device in a first group comprising a first plurality of storage media devices; and

write or read the second data part and the second computed ECC part in another storage media device in a second group comprising a second plurality of storage media devices;

wherein a first storage interface comprises first logic provide a first path between the first storage media and the first ECC engine for the first data part and first computed ECC part;

wherein the second storage interface comprises second logic to provide a second path between the second storage media and the second ECC engine for the second data part and second computed ECC part.

50. The article of manufacture of claim 49, wherein the ECC operations are performed in a first storage interface controller in a first chip and in a second storage interface controller in a second chip.