Memory controller and operating method of memory controller

• US 9,043,677 B2
• Filed: 03/03/2014
• Issued: 05/26/2015
• Est. Priority Date: 05/09/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kong, JaePhil, Cho, Yongwon, Song, Jong-Uk
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US14/194,993
• Publication Number:
  US 20140181589A1
• Time in Patent Office: 449 Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/1545 Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial
• CPC Class Codes: H03M 13/1555 Pipelined decoder implementations
• CPC Class Codes: H03M 13/3715 Adaptation to the number of estimated errors or to the channel state
• CPC Class Codes: H03M 13/6502 Reduction of hardware complexity or efficient processing

Abstract

A method of operating a memory controller to control a memory device includes reading a read vector from the memory device and correcting one or more errors in the read vector, where a power consumed at the correcting is varied according to the number of errors in the read vector.

Claims

1. A method of operating a memory controller to control a memory device, the method comprising:

reading data that comprises a data portion and a parity portion from the memory device;

determining a condition of the data portion based on the read data; and

performing a data processing i) only for the data portion if the condition of the data portion is good and the parity portion is not needed, ii) for both the data portion and the parity portion if the condition of the data portion is bad and both the data portion and the parity portion are needed, or iii) only for the data portion if the condition of the data portion is bad and only the data portion is needed.

2. The method of claim 1, wherein power consumption of the memory controller when the data processing is performed only for the data portion is less than power consumption of the memory controller when the data processing is performed for both the data portion and the parity portion.

3. The method of claim 1, wherein an operating cycle of the data processing performed only for the data portion is less than an operating cycle of the data processing performed for both the data portion and the parity portion.

4. The method of claim 1, wherein only the data portion is needed when a number of defects within the data portion is a first value, and both the data portion and the parity portion are needed when the number is a second value higher than the first value.

5. The method of claim 1, wherein the data processing comprises an error search.

6. The method of claim 5, further comprising correcting the data based on the performed error search.

7. The method of claim 5, wherein the error search is a forward chien search.

8. A memory system comprising:

a non-volatile memory NVM; and

a memory controller configured to read data that comprises a data portion and a parity portion from the NVM, determine a condition of the data portion based on the read data, and perform a data processing i) only for the data portion if the condition of the data portion is good and the parity portion is not needed, ii) for both the data portion and the parity portion if the condition of the data portion is bad and both the data portion and the parity portion are needed, or iii) only for the data portion if the condition of the data portion is bad and only the data portion is needed.

9. The memory system of claim 8, wherein power consumption of the memory controller when the data processing is performed only for the data portion is less than power consumption of the memory controller when the data processing is performed for both the data portion and the parity portion.

10. The memory system of claim 8, wherein an operating cycle of the data processing performed only for the data portion is less than an operating cycle of the data processing performed for both the data portion and the parity portion.

11. The memory system of claim 8, wherein only the data portion is needed when a number of defects within the data portion is a first value, and both the data portion and the parity portion are needed when the number is a second value higher than the first value.

12. The memory system of claim 8, wherein the data processing comprises an error search.

13. The memory system of claim 12, wherein the memory controller comprises an error correcting code ECC decoder configured to perform the read and the error search, and correct the read data based on the performed error search.

14. The memory controller of claim 12, wherein the error search is a forward chien search.

15. A computing device comprising a solid state drive SSD, the wherein the SSD comprises:

a first plurality of non-volatile memory NVM chips configured to communicate across a first channel;

a second plurality of NVM chips configured to communicate across a second channel independent of the first channel;

a memory controller configured to read data that comprises a data portion and a parity portion across each channel from a corresponding NVM chip, determine a condition based on the read data, and perform a data processing i) only for the data portion if the condition of the data portion is good and the parity portion is not needed, ii) for both the data portion and the parity portion if the condition of the data portion is bad and both the data portion and the parity portion are needed, or iii) only for the data portion if the condition of the data portion is bad and only the data portion is needed.

16. The computing system of claim 15, wherein power consumption of the memory controller when the data processing is performed only for the data portion is less than power consumption of the memory controller when the data processing is performed for both the data portion and the parity portion.

17. The computing system of claim 15, wherein an operating cycle of the data processing performed only for the data portion is less than an operating cycle of the data processing performed for both the data portion and the parity portion.

18. The computing device of claim 15, wherein only the data portion is needed when a number of defects within the data portion is a first value, and both the data portion and the parity portion are needed when the number is a second value higher than the first value.

19. The computing device of claim 15, wherein the data processing comprises an error search.

20. The computing system of claim 19, wherein the memory controller corrects the data based on the performed error search.

21. The computing device of claim 19, wherein the error search is a forward chien search.