Reconfigurable processor and method
First Claim
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1. A reconfigurable processor comprising:
- a plurality of memories divided into a plurality of different areas, the different divided areas corresponding to respective different threads from a plurality of threads and with sizes proportional to the respective different threads, with corresponding areas of the different divided areas storing context information of the respective different threads; and
a plurality of function units to perform a corresponding calculation based on received context information stored in an area, from the different divided areas, corresponding to a respective thread indicated to be executed,wherein the plurality of memories include a plurality of local register files each divided into a plurality of local register file areas, where each local register file area of a local register file is respectively configured to collectively store information for different threads from a particular function unit configured to execute the different threads, with the particular function unit being paired with the local register file distinguished from a different particular function unit paired with a different local register file, andwherein the plurality of memories receive identification information of the respective thread to be executed and make available to the plurality of function units the area, the area being mapped to the identification information.
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Abstract
Disclosed are a reconfigurable processor and processing method, a reconfiguration control apparatus and method, and a thread modeler and modeling method. A memory area of a reconfigurable processor may be divided into a plurality of areas, and a context enabling a thread process may be stored in respective divided areas, in advance. Accordingly, when a context switching is performed from one thread to another thread, the other thread may be executed by using information stored in an area corresponding to the other thread.
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Citations
31 Claims
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1. A reconfigurable processor comprising:
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a plurality of memories divided into a plurality of different areas, the different divided areas corresponding to respective different threads from a plurality of threads and with sizes proportional to the respective different threads, with corresponding areas of the different divided areas storing context information of the respective different threads; and a plurality of function units to perform a corresponding calculation based on received context information stored in an area, from the different divided areas, corresponding to a respective thread indicated to be executed, wherein the plurality of memories include a plurality of local register files each divided into a plurality of local register file areas, where each local register file area of a local register file is respectively configured to collectively store information for different threads from a particular function unit configured to execute the different threads, with the particular function unit being paired with the local register file distinguished from a different particular function unit paired with a different local register file, and wherein the plurality of memories receive identification information of the respective thread to be executed and make available to the plurality of function units the area, the area being mapped to the identification information. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A reconfigurable processor comprising:
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a plurality of memories divided into a plurality of different areas, the different divided areas corresponding to respective different threads from a plurality of threads and with sizes proportional to the respective different threads, with corresponding areas of the different divided areas storing context information of the respective different threads; and a plurality of function units to perform a corresponding calculation based on received context information stored in an area, from the different divided areas, corresponding to a respective thread indicated to be executed, wherein the plurality of memories comprise; at least one global register file divided into a plurality of global register file areas corresponding to the respective different threads from the plurality of threads, to provide, to the plurality of function units, an input value loaded to an area of the plurality of divided global register file areas corresponding to the respective thread to be executed; and a plurality of local register files each divided into a plurality of local register file areas corresponding to the respective different threads from the plurality of threads, to each store, in a respective area of each of the plurality of divided local register file areas corresponding to the respective thread to be executed, a respective output value of a calculation performed by a respective function unit, and wherein the plurality of memories receive identification information of the respective thread to be executed and make available to the plurality of function units the area, the area being mapped to the identification information. - View Dependent Claims (9)
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10. A reconfiguration control apparatus comprising:
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a reconfigurable processor having a plurality of memories divided into a plurality of different areas, the different divided areas corresponding to respective different threads from a plurality of threads and with sizes proportional to the respective different threads, and to store context information of the respective different threads in corresponding areas of the different divided areas; and a controlling unit to control a storing of the context information of the respective different threads in the corresponding different divided areas, wherein the plurality of memories include a plurality of local register files each divided into a plurality of local register file areas, where each local register file area of a local register file is respectively configured to collectively store information for different threads from a particular function unit of the reconfigurable processor configured to execute the different threads, with the particular function unit being paired with the local register file distinguished from a different particular function unit of the reconfigurable processor paired with a different local register file, and wherein the plurality of memories receive identification information of the respective thread to be executed and make available to the plurality of function units the area, the area being mapped to the identification information. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A reconfiguration control method comprising:
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dividing a plurality of memories included in a reconfigurable processor into a plurality of different divided areas corresponding to respective different threads from a plurality of threads and with sizes proportional to the respective different threads; and storing context information of the respective different threads in corresponding areas of the different divided areas, wherein the plurality of memories include a plurality of local register files each divided into a plurality of local register file areas, where each local register file area of a local register file is respectively configured to collectively store information for different threads from a particular function unit of a reconfigurable processor configured to execute the different threads, with the particular function unit being paired with the local register file distinguished from a different particular function unit of the reconfigurable processor paired with a different local register file, and wherein the plurality of memories receive identification information of the respective thread to be executed and make available to the plurality of function units the area the area being mapped to the identification information. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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24. A thread modeling method comprising:
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calling a plurality of Kernel functions, and setting input datasets corresponding to the plurality of Kernel functions as respective threads, respectively; performing context switching from a thread of the respective threads currently set to be executed to another thread of the respective threads, while maintaining a local register file of each of plural respectively paired function units respectively configured to execute the respective threads and with sizes proportional to the respective threads, and executing the other thread upon a stall occurring with respect to the thread of the respective threads currently set to be executed; and maintaining a global register file separate from the local register file, wherein each local register file is configured to maintain, upon the stall, collective storage of information for different threads from a respectively paired function unit, of the plural function units, configured to execute the different threads in different divided areas of each local register file, with each divided area being mapped to a different thread, and wherein the local resister files receive identification information of the respective thread to be executed and make available to the plurality of function units the area, the area being mapped to the identification information. - View Dependent Claims (25, 26, 27)
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28. A thread modeling method comprising:
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calling a Kernel function, and dividing input datasets corresponding to the called Kernel function; setting the divided input datasets as respective threads; performing context switching from a thread of the respective threads currently set to be executed to another thread of the respective threads, while maintaining a local register file of each of plural respectively paired function units respectively configured to execute the respective threads and with sizes proportional to the respective threads, corresponding to an input dataset of the divided input datasets different from an input dataset set as the thread currently set to be executed, and executing the other thread upon a stall occurring with respect to the thread of the respective threads currently set to be executed, wherein each local register file is configured to maintain, upon the stall, collective storage of information for different threads from a respectively paired function unit, of the plural function units, configured to execute the different threads in different divided areas of each local register file, with each divided area being mapped to a different thread, and wherein the local register files receive identification information of the respective thread to be executed and make available to the plurality of function units the area the area being mapped to the identification information. - View Dependent Claims (29, 30, 31)
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Specification