Compliant bipolar micro device transfer head with silicon electrodes

• US 9,044,926 B2
• Filed: 03/20/2014
• Issued: 06/02/2015
• Est. Priority Date: 07/06/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Golda, Dariusz, Bibl, Andreas
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US14/221,071
• Publication Number:
  US 20140209248A1
• Time in Patent Office: 439 Days
• Field of Search: 257/774, 257/623, 257/619, 257/E29.324, 257/739, 257/E21.585, 257/E23.174, 257/621, 257/288, 438/39, 438/130, 438/158, 438/250, 438/619, 438/637, 438/703, 438/739, 438/126, 438/128, 438/251, 438/390
• US Class Current: 1/1
• CPC Class Codes: B32B 38/18 Handling of layers or the laminate
• CPC Class Codes: B81C 99/002 Apparatus for assembling MEMS, e.g. micromanipulators micromanipulators per se B25J7/00
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 2224/7598 specially adapted for batch processes
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H02N 13/00 : Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect
• CPC Class Codes: Y10T 156/17 : Surface bonding means and/or assemblymeans with work feeding or handling means

Abstract

A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.

Claims

1. A bipolar micro device transfer head array comprising:

a base substrate;

an array of electrostatic transfer heads, each electrostatic transfer head including a pair of silicon electrodes that is deflectable into a cavity between the base substrate and the pair of silicon electrodes, and a dielectric material covering a top surface of the pair of silicon electrodes.

2. The micro device transfer head array of claim 1, wherein each pair of silicon electrodes is deflectable into the same cavity.

3. The micro device transfer head array of claim 2, wherein the cavity is in the base substrate.

4. The micro device transfer head array of claim 1, wherein each pair of silicon electrodes is deflectable into a separate cavity.

5. The micro device transfer head array of claim 4, wherein each separate cavity is in the base substrate.

6. The micro device transfer head array of claim 1, wherein the array of electrostatic transfer heads comprises:

a first array of silicon electrodes in electrical connection with a first bus interconnect; and

a second array of silicon electrodes in electrical connection with a second bus interconnect.

7. The micro device transfer head array of claim 6, wherein the array of electrostatic transfer heads comprises:

a first plurality of trace interconnects electrically connecting the first array of silicon electrodes with the first bus interconnect; and

a second plurality of trace interconnects electrically connecting the second array of silicon electrodes with the second bus interconnect.

8. The micro device transfer head array of claim 7, wherein the first and second plurality of trace interconnects are silicon trace interconnects, and the first and second bus interconnects are silicon bus interconnects.

9. The micro device transfer head array of claim 6, further comprising a first voltage source connection in electrical connection with the first bus interconnect, and a second voltage source connection in electrical connection with the second bus interconnect.

10. The micro device transfer head array of claim 9, wherein the first voltage source connection comprises a via extending through the first bus interconnect and the base substrate, and the second voltage source connection comprises a via extending through the second bus interconnect and the base substrate.

11. The micro device transfer head array of claim 1, wherein each electrostatic transfer head is configured to pick up an individual micro device of 1 to 100 μ

m scale.

12. The micro device transfer head of claim 1, wherein the dielectric material covering the top surface of the pair of silicon electrodes has a thickness between 0.5-10 μ

m.

13. The micro device transfer head of claim 1, wherein each silicon electrode includes a silicon electrode lead and a silicon mesa structure.

14. The micro device transfer head of claim 13, wherein the mesa structure is less than 20 μ

m thick.

15. The micro device transfer head of claim 13, wherein the mesa structure is less than 10 μ

m thick.

16. The micro device transfer head of claim 1, wherein each silicon electrode is doped.

17. The micro device transfer head of claim 1, further comprising an oxide layer on a bottom surface of the pair of silicon electrodes.

18. The micro device transfer head of claim 1, wherein the dielectric material comprises an oxide selected from the group consisting of SiO₂, Al₂O₃, Ta₂O₅, HfO₂, and RuO₂.