Method and apparatus for limiting access to an integrated circuit (IC)
First Claim
1. A method comprising:
- a) determining at an integrated circuit (IC) if a clock frequency of a clock signal at the IC is abnormal by virtue of being slower than a specified lower clock frequency limit;
b) determining at the IC if the clock frequency is abnormal by virtue of being faster than a specified upper clock frequency limit;
c) determining at the IC if the clock frequency is abnormal by virtue of the clock signal having stopped;
utilizing at least one bandgap reference for the determining if the clock frequency is slower than the specified lower clock frequency limit and for determining if the clock frequency is faster than the specified upper clock frequency limit, wherein the utilizing the bandgap reference comprises utilizing a sampled bandgap reference, wherein the sampled bandgap reference is refreshed to maintain accuracy of the bandgap reference; and
limiting access to the IC in response to determining the clock frequency is abnormal by at least one of a), b), and c).
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Accused Products
Abstract
A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.
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Citations
18 Claims
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1. A method comprising:
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a) determining at an integrated circuit (IC) if a clock frequency of a clock signal at the IC is abnormal by virtue of being slower than a specified lower clock frequency limit; b) determining at the IC if the clock frequency is abnormal by virtue of being faster than a specified upper clock frequency limit; c) determining at the IC if the clock frequency is abnormal by virtue of the clock signal having stopped; utilizing at least one bandgap reference for the determining if the clock frequency is slower than the specified lower clock frequency limit and for determining if the clock frequency is faster than the specified upper clock frequency limit, wherein the utilizing the bandgap reference comprises utilizing a sampled bandgap reference, wherein the sampled bandgap reference is refreshed to maintain accuracy of the bandgap reference; and limiting access to the IC in response to determining the clock frequency is abnormal by at least one of a), b), and c). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An integrated circuit (IC) comprising:
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a clock detector, the clock detector comprising; a low clock frequency detector to detect if a clock signal at a node of the IC is abnormal by virtue of a frequency of the clock signal being below a specified lower limit; a high clock frequency detector to detect if the clock signal at the node is abnormal by virtue of the frequency of the clock signal being above a specified upper limit; at least one sampled bandgap reference for the determining if the frequency of the clock signal is below the specified lower limit and for determining if the frequency of the clock signal is above the specified upper limit, wherein the sampled bandgap reference is refreshed to maintain accuracy of the bandgap reference; a stopped clock detector to detect if the clock signal at the node is abnormal by virtue of the clock signal being stopped; and a tamper controller to limit access to the IC in response to determining the clock signal is abnormal. - View Dependent Claims (15, 16, 17)
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18. A method comprising:
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a) determining at an integrated circuit (IC) if a clock frequency of a clock signal at the IC is abnormal by virtue of being slower than a specified lower clock frequency limit; b) determining at the IC if the clock frequency is abnormal by virtue of being faster than a specified upper clock frequency limit; c) determining at the IC if the clock frequency is abnormal by virtue of the clock signal having stopped; utilizing at least one bandgap reference for the determining if the clock frequency is slower than the specified lower clock frequency limit and for determining if the clock frequency is faster than the specified upper clock frequency limit, wherein the utilizing the bandgap reference consumes an average power of less than five microwatts; and limiting access to the IC in response to determining the clock frequency is abnormal by at least one of a), b), and c).
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Specification