Reducing penalties for cache accessing operations

• US 9,047,199 B2
• Filed: 12/03/2013
• Issued: 06/02/2015
• Est. Priority Date: 06/14/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fee, Michael F., Jones, Christine C., O'Neill, Arthur J., Orf, Diane L.
• Primary Examiner(s): Islam, Mohammad
• Assistant Examiner(s): LIU, MIKKA H
• Application Number:
  US14/095,385
• Publication Number:
  US 20140095795A1
• Time in Patent Office: 546 Days
• Field of Search: 711/105, 711/118, 711/E12.017, 711/E12.001
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0846 Cache with multiple tag or data arrays being simultaneously accessible
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer program product for reducing penalties for cache accessing operations is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes respectively associating platform registers with cache arrays, loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, and, based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.

Claims

1. A system for reducing penalties for cache accessing operations, the system comprising:

cache arrays and platform registers respectively associated with the cache arrays, the system configured to perform a method comprising;

loading control information and data of first and second store operations, which are respectively passing through first and second pipe passages and which are to be executed with respect to one or more of the cache arrays, into the one or more of the platform registers respectively associated with the one or more of the cache arrays in an event the first and second store operations are targeting a same wordline of the one or more of the cache arrays,

the loading being conducted by way of respective couplings between the first and second pipe passages and the one or more of the platform registers; and

based on the one or more of the cache arrays becoming available, committing the data of the first and second store operations from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays at a same time.

2. The system according to claim 1, wherein the platform registers are disposed proximate to the respectively associated cache arrays.

3. The system according to claim 2, wherein the cache arrays comprise dynamic random access memory (DRAM) or embedded dynamic random access memory (eDRAM).

4. The system according to claim 1, wherein the method further comprises:

receiving respective instructions to execute the first and second store operations;

analyzing the first and second store operations; and

identifying the same wordline of the one or more of the cache arrays with respect to which the first and second store operations are to be executed in accordance with results of the analyzing,

wherein the analyzing comprises;

comparing target wordlines respectively associated with the first and second store operations; and

delaying a start of an earlier one of the first and second store operations until the loading of the later one of the first and second store operations is complete in an event the target wordlines are the same wordline.

5. The system according to claim 1, wherein the control information comprises addresses and identification information of the one or more of the cache arrays.

6. The system according to claim 1, wherein the method further comprises determining that the one or more of the cache arrays is available.

7. The system according to claim 6, wherein the determining is conducted with the control information loaded into the one or more of the platform registers.

8. The system according to claim 1, wherein the method further comprises:

completing the committing of the data using the control information; and

making the one or more of the platform registers available for other store operations.

9. A system comprising cache arrays and platform registers respectively associated with the cache arrays, the system being configured to:

load control information and data of first and second store operations, which are respectively passing through first and second pipe passages and which are to be executed with respect to one or more of the cache arrays, into the one or more of the platform registers respectively associated with the one or more of the cache arrays in an event the first and second store operations are targeting a same wordline of the one or more of the cache arrays,

the load being conducted by way of respective couplings between the first and second pipe passages and the one or more of the platform registers; and

based on the one or more of the cache arrays becoming available, commit the data of the first and second store operations from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays at a same time.

10. The system according to claim 9, wherein the platform registers are disposed proximate to the respectively associated cache arrays.

11. The system according to claim 10, wherein the cache arrays comprise dynamic random access memory (DRAM) or embedded dynamic random access memory (eDRAM).

12. The system according to claim 9, wherein the system is further configured to:

receive an instruction to execute the first and second store operations;

analyze the first and second store operations; and

identify the same wordline of the one or more of the cache arrays with respect to which the first and second store operations are to be executed in accordance with results of the analyzing,

wherein the analyzing comprises;

comparing target wordlines respectively associated with the first and second store operations; and

delaying a start of an earlier one of the first and second store operations until the loading of the later one of the first and second store operations is complete in an event the target wordlines are the same wordline.

13. The system according to claim 9, wherein the control information comprises addresses and identification information of the one or more of the cache arrays.

14. The system according to claim 9, wherein the system is further configured to determine that the one or more of the cache arrays is available.

15. The system according to claim 14, wherein the determine is conducted with the control information loaded into the one or more of the platform registers.

16. The system according to claim 9, wherein the system is further configured to:

complete the committing of the data using the control information; and

make the one or more of the platform registers available for other store operations.