Techniques to perform forward error correction for an electrical backplane

• US 9,047,204 B2
• Filed: 01/03/2013
• Issued: 06/02/2015
• Est. Priority Date: 01/04/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ganga, Ilango S., Chang, Luke, Belogolovy, Andrey, Ovchinnikov, Andrei
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US13/733,271
• Publication Number:
  US 20140019827A1
• Time in Patent Office: 880 Days
• Field of Search: 714/752, 714/775, 714/789, 714/798, 714/799
• US Class Current: 1/1
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: H03M 13/33 Synchronisation based on error coding or decoding
• CPC Class Codes: H03M 13/63 Joint error correction and other techniques H03M13/31 and H03M13/33 take precedence
• CPC Class Codes: H03M 13/6312 Error control coding in combination with data compression
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0058 Block-coded modulation
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: Y02D 30/00 Reducing energy consumption in communication networks

Abstract

Techniques to perform forward error correction for an electrical backplane are described including forward error correction (FEC) circuitry to perform forward error correction, physical coding sublayer circuitry, and physical medium attachment (PMA) circuitry. The FEC circuitry provides primitives comprising a FEC_UNITDATA.request primitive, a FEC_UNITDATA.signal primitive, and FEC_UNITDATA.indication primitive, the FEC sublayer and includes an encoder having a reverse gearbox and a pseudo-noise generator.

Claims

1. An apparatus, comprising:

a media independent interface; and

circuitry comprising forward error correction (FEC) circuitry to perform forward error correction, physical coding sublayer circuitry, and physical medium attachment (PMA) circuitry, the FEC circuitry to provide operations corresponding to primitives comprising;

a FEC_UNITDATA.request primitive to identify a tx-data-group to scramble and to cause the FEC circuitry to transfer scrambled tx-data-group data to the physical medium attachment circuitry,

a FEC-SIGNAL.indication primitive capable to indicate successful delineation of valid payload information from a data stream from the physical medium attachment circuitry and, alternately, to indicate error detection, and

a FEC_UNITDATA.indication primitive to identify an rx-data-group to the physical coding sublayer circuitry, the FEC circuitry comprising an encoder having a pseudo-noise generator.

2. The apparatus of claim 1, wherein the FEC circuitry comprises a processor.

3. The apparatus of claim 1, wherein the FEC circuitry comprises a plurality of hardware components forming a part of a hardware physical layer unit.

4. The apparatus of claim 1, further comprising a MAC (Media Access Control).

5. The apparatus of claim 1, further comprising memory and a processor.

6. The apparatus of claim 1, where in the apparatus comprises a PHY.