Logical cell array and bus system
First Claim
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1. A data processor on a chip comprising:
- a plurality of processing array elements disposed in a multi-dimensional array, the processing array elements including a plurality of data processing units comprising arithmetic logic units operative to perform one or more of a plurality of arithmetic operand functions and a plurality of memory units in operative communication with the plurality of arithmetic logic units, wherein the data processing units within a first axis of the multi-dimensional array are in communication with the memory units within the first axis of the multi-dimensional array;
at least one interface unit operative to provide at least one communication channel between the plurality of processing array elements;
a bus system flexibly interconnecting the plurality of processing array elements for multi-directional communication across the bus system among the plurality of processing array elements.
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Abstract
A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
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Citations
11 Claims
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1. A data processor on a chip comprising:
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a plurality of processing array elements disposed in a multi-dimensional array, the processing array elements including a plurality of data processing units comprising arithmetic logic units operative to perform one or more of a plurality of arithmetic operand functions and a plurality of memory units in operative communication with the plurality of arithmetic logic units, wherein the data processing units within a first axis of the multi-dimensional array are in communication with the memory units within the first axis of the multi-dimensional array; at least one interface unit operative to provide at least one communication channel between the plurality of processing array elements; a bus system flexibly interconnecting the plurality of processing array elements for multi-directional communication across the bus system among the plurality of processing array elements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A data processor on a chip comprising:
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a plurality of processing array elements disposed in a multi-dimensional array, the processing array elements including a plurality of arithmetic logic units operative to perform one or more of a plurality of arithmetic operand functions and a plurality of memory units in operative communication with the plurality of arithmetic logic units; at least one interface unit operative to provide at least one communication channel between the plurality of processing array elements; a bus system flexibly interconnecting the plurality of processing array elements for multi-directional communication across the bus system among the plurality of processing array elements.
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Specification