Display device and electronic device
First Claim
Patent Images
1. A display device comprising:
- a pixel portion comprising pixels arranged in matrix wherein each of the pixels includes a transistor and a display element;
a gate driver electrically connected to a gate of the transistor;
a source driver electrically connected to one of a source and a drain of the transistor; and
a data processing circuit configured to output signals to the source driver, wherein the transistor has a channel formation region including an oxide semiconductor, wherein the data processing circuit is configured to output the signals by using n-bit digital data of input m-bit digital data for voltage gradation and by using (m−
n) bit digital data for time gradation,wherein m and n are positive integers, where m>
n, andwherein an off-state current per unit channel width of the transistor is 10 aA/.mu.m or less.
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Abstract
Multiple gray levels are expressed in a display device. The display device includes a pixel portion where pixels including transistors and display elements are arranged in matrix, a gate driver electrically connected to a gate of the transistor, a source driver electrically connected to a source or a drain of the transistor, and a data processing circuit which outputs a signal to the source driver. The transistor includes an oxide semiconductor. In the data processing circuit, n-bit digital data of input m-bit digital data (m and n are positive integers, where m>n) is used for voltage gradation and (m−n) bit digital data is used for time gradation.
137 Citations
33 Claims
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1. A display device comprising:
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a pixel portion comprising pixels arranged in matrix wherein each of the pixels includes a transistor and a display element; a gate driver electrically connected to a gate of the transistor; a source driver electrically connected to one of a source and a drain of the transistor; and a data processing circuit configured to output signals to the source driver, wherein the transistor has a channel formation region including an oxide semiconductor, wherein the data processing circuit is configured to output the signals by using n-bit digital data of input m-bit digital data for voltage gradation and by using (m−
n) bit digital data for time gradation,wherein m and n are positive integers, where m>
n, andwherein an off-state current per unit channel width of the transistor is 10 aA/.mu.m or less. - View Dependent Claims (2, 3, 4, 5, 6, 7, 30)
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8. A display device comprising:
- a pixel portion comprising pixels arranged in matrix wherein each of the pixels includes a transistor and a display element;
a gate driver electrically connected to a gate of the transistor; a source driver electrically connected to one of a source and a drain of the transistor; and a data processing circuit configured to output signals to the source driver, wherein the transistor has a channel formation region including an intrinsic or substantially intrinsic oxide semiconductor, wherein the data processing circuit is configured to output the signals by using n-bit digital data of input m-bit digital data for voltage gradation and by using (m−
n) bit digital data for time gradation,wherein m and n are positive integers, where m>
n, andwherein an off-state current per unit channel width of the transistor is 10 aA/.mu.m or less. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 31)
- a pixel portion comprising pixels arranged in matrix wherein each of the pixels includes a transistor and a display element;
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16. A display device comprising:
- a pixel portion comprising pixels arranged in matrix wherein each of the pixels includes a transistor and a display element;
a gate driver electrically connected to a gate of the transistor; a source driver electrically connected to one of a source and a drain of the transistor; and a data processing circuit configured to output signals to the source driver, wherein the transistor has a channel formation region including an oxide semiconductor and has an off-state current of 1 aA/.mu.m or less, wherein in the data processing circuit is configured to process n-bit digital data of input m-bit digital data as data related to voltage gradation and to process (m−
n) bit digital data as data related to time gradation,wherein m and n are positive integers, where m>
n,wherein the signals are output to the source driver through a switch in the data processing circuit, and wherein an off-state current per unit channel width of the transistor is 10 aA/.mu.m or less. - View Dependent Claims (17, 18, 19, 20, 21, 22, 32)
- a pixel portion comprising pixels arranged in matrix wherein each of the pixels includes a transistor and a display element;
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23. A display device comprising:
- a pixel portion comprising pixels arranged in matrix wherein each of the pixels includes a transistor and a display element;
a gate driver electrically connected to a gate of the transistor; a source driver electrically connected to one of a source and a drain of the transistor; and a data processing circuit, wherein the transistor has a channel formation region including an oxide semiconductor, wherein the data processing circuit is configured to select two voltage levels, which is to be output from the source driver, among (n−
1) voltage levels based on n-bit digital data of input m-bit digital data, wherein the data processing circuit is configured to output 2.sup.m-n digital data for one pixel in one frame period to the source driver where each of the 2.sup.m-n digital data is selected from either of two digital data corresponding to the two voltage levels, and wherein m and n are positive integers, where m>
n, andwherein an off-state current per unit channel width of the transistor is 10 aA/.mu.m or less. - View Dependent Claims (24, 25, 26, 27, 28, 29, 33)
- a pixel portion comprising pixels arranged in matrix wherein each of the pixels includes a transistor and a display element;
Specification