Resistive random access memory cells having variable switching characteristics

• US 9,047,940 B2
• Filed: 01/10/2013
• Issued: 06/02/2015
• Est. Priority Date: 01/10/2013
• Status: Expired due to Fees

• Current Assignee: Intermolecular Incorporated (Merck & Co., Inc.), Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Intermolecular Incorporated (Merck & Co., Inc.), Kabushiki Kaisha Toshiba (Toshiba Corporation), SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Wang, Yun, Nardi, Federico
• Primary Examiner(s): Tran, Anthan
• Application Number:
  US13/738,524
• Publication Number:
  US 20140192586A1
• Time in Patent Office: 873 Days
• Field of Search: 365/148, 365/158
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 2213/12 Non-metal ion trapping, i.e. using memory material trapping non-metal ions given by the electrode or another layer during a write operation, e.g. trapping, doping
• CPC Class Codes: G11C 2213/15 Current-voltage curve
• CPC Class Codes: G11C 2213/52 Structure characterized by the electrode material, shape, etc.
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/883 Oxides or nitrides
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels
• CPC Class Codes: H10N 70/8845 Carbon or carbides

Abstract

Provided are resistive random access memory (ReRAM) cells forming arrays and methods of operating such cells and arrays. The ReRAM cells of the same array may have the same structure, such as have the same bottom electrodes, top electrodes, and resistive switching layers. Yet, these cells may be operated in a different manner. For example, some ReRAM cells may be restively switched using lower switching voltages than other cells. The cells may also have different data retention characteristics. These differences may be achieved by using different forming operations for different cells or, more specifically, flowing forming currents in different directions for different cells. The resulting conductive paths formed within the resistive switching layers are believed to switch at or near different electrode interfaces, i.e., within a so called switching zone. In some embodiments, a switching zone of a ReRAM cell may be changed even after the initial formation.

Claims

1. A method comprising:

providing a first resistive random access memory (ReRAM) cell,

the first ReRAM cell comprising a top electrode, a bottom electrode, and a resistive switching layer disposed between the top electrode and the bottom electrode,

the top electrode having a different composition than the bottom electrode;

setting an initial conductive path through the resistive switching layer of the first ReRAM cell,

wherein the forming the initial conductive path comprises

passing an electrical current in a direction from the top electrode to the bottom electrode of the first ReRAM cell,

wherein a resistance of the resistive switching layer decreases while the electrical current is passed in the direction from the top electrode to the bottom electrode of the first ReRAM cell and the initial conductive path is set through the resistive switching layer;

breaking the initial conductive path within the resistive switching layer of the first ReRAM cell,

wherein the breaking comprises passing an electrical current in a direction from the bottom electrode to the top electrode of the first ReRAM cell,

wherein the resistance of the resistive switching layer increases while the electrical current is passed in the direction from the bottom electrode to the top electrode of the first ReRAM cell and the initial conductive path is broken within the resistive switching layer; and

setting a new conductive path through the resistive switching layer of the first ReRAM cell,

wherein setting the new conductive path comprises passing an electrical current in a direction from the bottom electrode to the top electrode of the first ReRAM cell,

wherein the resistance of the resistive switching layer decreases while the electrical current is passed in the direction from the bottom electrode to the top electrode of the first ReRAM cell and the new conductive path is set through the resistive switching layer.

2. The method of claim 1, wherein the resistance of the resistive switching layer having the initial conductive path of the first ReRAM cell is different from the resistance of the resistive switching layer having the new conductive path.

3. The method of claim 2, wherein the resistance of the resistive switching layer having the initial conductive path of the first ReRAM cell is less than a half of the resistance of the resistive switching layer having the new conductive path.

4. The method of claim 1, further comprising:

breaking the new conductive path through the resistive switching layer of the first ReRAM cell,

wherein the breaking comprises passing an electrical current in a direction from the top electrode to the bottom electrode of the first ReRAM cell, and

wherein the resistance of the resistive switching layer increases while the electrical current is passed in the direction from the top electrode to the bottom electrode of the first ReRAM cell and the new conductive path is broken within the resistive switching layer.

5. The method of claim 4, wherein a total power used for breaking the initial conductive path through the resistive switching layer of the first ReRAM cell is different from a total power used for breaking the new conductive path through the resistive switching layer of the first ReRAM cell.

6. The method of claim 5, wherein the total power used for breaking the initial conductive path through the resistive switching layer of the first ReRAM cell is less than a half of the total power used for breaking the new conductive path through the resistive switching layer of the first ReRAM cell.

7. The method of claim 1, wherein a total power used for setting the new conductive path through the resistive switching layer of the first ReRAM cell is different from a total power used for setting the initial conductive path through the resistive switching layer of the first ReRAM cell.

8. The method of claim 7, wherein the total power used for setting the new conductive path through the resistive switching layer of the first ReRAM cell is less than a half of the total power used for setting the initial conductive path through the resistive switching layer of the first ReRAM cell.

9. The method of claim 1, wherein the top electrode of the first ReRAM cell comprises titanium nitride and wherein the bottom electrode of the first ReRAM cell comprises doped polysilicon.

10. The method of claim 9, wherein the bottom electrode of the first ReRAM cell comprises n-doped polysilicon.

11. The method of claim 1, wherein the resistive switching layer of the first ReRAM cell comprises hafnium oxide.

12. The method of claim 1, wherein the resistive switching layer of the first ReRAM cell has a first composition at its interface with the top electrode and a second composition at its interface with the second electrode, and wherein the first composition is different from the second composition.

13. The method of claim 1, wherein the resistive switching layer of the first ReRAM cell is a bi-layer.

14. The method of claim 13, wherein the bi-layer comprises two sub-layers having different compositions.