Word line coupling for deep program-verify, erase-verify and read

• US 9,047,970 B2
• Filed: 10/28/2013
• Issued: 06/02/2015
• Est. Priority Date: 10/28/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Wan, Jun, Pan, Feng, Lei, Bo
• Primary Examiner(s): Lam, David
• Application Number:
  US14/065,092
• Publication Number:
  US 20150117114A1
• Time in Patent Office: 582 Days
• Field of Search: 365/185.21, 365/185.23, 365/185.18, 365/230.06
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

In a non-volatile storage system, a reduced voltage is provided on a selected word line during a sensing operation, using down coupling from one or more adjacent word lines. Voltages of one or more adjacent word lines of a selected word line are driven down while a voltage of the selected word line is floated. Capacitive coupling from the one or more adjacent word lines to the selected word line reduces the voltage of the selected word line. The capacitive coupling can be provided during a read, a program-verify test or an erase-verify test. The erase-verify test can be performed on cells of even-numbered word lines while capacitive coupling is provided by odd-numbered word lines, or on cells of odd-numbered word lines while capacitive coupling is provided by even-numbered word lines. Voltages of non-adjacent word lines can be provided at fixed, pass voltage levels.

Claims

1. A method for sensing in a memory device, comprising:

driving a selected word line of a plurality of word lines at a driven level, each word line of the plurality of word lines is connected to a respective memory cells in a set of memory cells;

down coupling the selected word line to a down coupled level, below the driven level, the down coupling comprises floating a voltage of the selected word line while decreasing a voltage of one or more adjacent word lines of the selected word line; and

while the voltage of the selected word line is floating and at the down coupled level, performing a sensing operation which involves the selected word line.

2. The method of claim 1, further comprising:

during the driving of the selected word line at the driven level, increasing the voltage of the one or more adjacent word lines.

3. The method of claim 1, wherein:

the driven level is a non-negative voltage; and

the down coupled level is a negative voltage.

4. The method of claim 1, wherein:

the driven level is a non-negative voltage; and

the down coupled level is a non-negative voltage.

5. The method of claim 1, wherein:

the driven level is a negative voltage; and

the down coupled level is a negative voltage.

6. The method of claim 1, wherein:

the voltage of the one or more adjacent word lines is decreased no further than a level which is sufficiently high to provide memory cells which are connected to the one or more adjacent word lines in a conductive state during the sensing operation.

7. The method of claim 1, wherein:

the one or more adjacent word lines comprise an erased word line which is after the selected word line in a programming order of the plurality of word lines, the erased word line is connected to erased memory cells and is not connected to programmed memory cells, and a programmed adjacent word line which is before the selected word line in the programming order of the plurality of word lines and is connected to programmed memory cells; and

the down coupling reduces voltages of the erased and programmed word lines to different respective minimum levels, the respective minimum level of the programmed adjacent word line is greater than the respective minimum level of the erased adjacent word line.

8. The method of claim 7, wherein:

the respective minimum level of the programmed adjacent word line is sufficiently high to provide the programmed memory cells in a conductive state during the sensing operation; and

the respective minimum level of the erased adjacent word line is sufficiently high to provide the erased memory cells in a conductive state during the sensing operation.

9. The method of claim 7, wherein:

an amount of down coupling from the erased adjacent word line is more than an amount of down coupling from the programmed adjacent word line.

10. The method of claim 1, wherein:

the sensing operation comprises an erase-verify operation for even-or-odd-numbered word lines of the plurality of word lines; and

each of the even-or-odd-numbered word lines is down coupled by at least one adjacent word line of the plurality of word lines in preparation for the performing of the sensing operation.

11. The method of claim 1, wherein:

the sensing operation comprises a program-verify operation or a read operation; and

one or more remaining word lines of the plurality of word lines, other than the one or more adjacent word lines, have a fixed voltage during the floating of the selected word line and do not down couple the selected word line.

12. A non-volatile storage apparatus, comprising:

a set of memory cells;

a plurality of word lines, each word line of the plurality of word lines is connected to respective memory cells in the set of memory cells, the plurality of word lines comprises a selected word line and one or more adjacent word lines of the selected word line;

a set of word line drivers comprising a word line driver connected to the selected word line, and one or more word line drivers connected to one or more adjacent word lines;

sensing circuitry associated with the set of memory cells; and

a control circuit associated with the set of word line drivers and the sensing circuitry, the control circuit;

causes the word line driver connected to the selected word line to drive the selected word line at a driven level,

to down couple the selected word line to a down coupled level, below the driven level, causes the word line driver connected to the selected word line to float a voltage of the selected word line while causing the one or more word line drivers connected to the one or more adjacent word lines to decrease a voltage of the one or more adjacent word lines, and

while the voltage of the selected word line floats and is at the down coupled level, cause the sensing circuitry to perform a sensing operation which involves the selected word line.

13. The non-volatile storage apparatus of claim 12, wherein:

the control circuit, during the driving of the selected word line at the driven level, causes the one or more word line drivers connected to the one or more adjacent word lines to increase the voltage of the one or more adjacent word lines.

14. The non-volatile storage apparatus of claim 12, wherein:

the one or more adjacent word lines comprise an erased word line which is after the selected word line in a programming order of the plurality of word lines, the erased word line is connected to erased memory cells and is not connected to programmed memory cells, and a programmed adjacent word line which is before the selected word line in the programming order of the plurality of word lines and is connected to programmed memory cells;

the down coupling reduces voltages of the erased and programmed word lines to different respective minimum levels, the respective minimum level of the programmed adjacent word line is greater than the respective minimum level of the erased adjacent word line; and

an amount of down coupling from the erased adjacent word line is more than an amount of down coupling from the programmed adjacent word line.

15. The non-volatile storage apparatus of claim 12, wherein:

the sensing operation comprises an erase-verify operation for even-or-odd-numbered word lines of the plurality of word lines; and

each of the even-or-odd-numbered word lines is down coupled by at least one adjacent word line of the plurality of word lines in preparation for the sensing operation.

16. The non-volatile storage apparatus of claim 12, wherein:

the set of memory cells is in a NAND configuration.

17. The non-volatile storage apparatus of claim 12, further comprising:

the set of memory cells is in a NOR configuration.

18. A method for sensing in a memory device, comprising:

in response to a command to perform a sensing operation involving a selected word line of a plurality of word lines, providing a voltage on the selected word line by initially driving the selected word line at a driven level and subsequently down coupling the selected word line to a down coupled level, below the driven level; and

while the voltage of the selected word line is floating and at the down coupled level, sensing a state of a memory cell connected to the selected word line.

19. The method of claim 18, wherein:

the driven level is a non-negative voltage; and

the down coupled level is a negative voltage.

20. The method of claim 18, wherein:

the down coupling of the selected word line is achieved using one or more adjacent word lines of the selected word line.