Group word line erase and erase-verify methods for 3D non-volatile memory
First Claim
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1. A method for performing an erase operation, comprising:
- charging a channel of an active area of a plurality of memory cells, the charging of the channel comprises applying an erase voltage to one end of the active area, the plurality of memory cells are formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the active area comprises a pillar which extends vertically in the three-dimensional non-volatile memory;
during the charging of the channel, setting control gate voltages of the plurality of memory cells to encourage erasing of the memory cells, the setting the control gate voltages is based on an assignment of the plurality of memory cells to different groups, each group of the different groups comprises multiple adjacent memory cells of the plurality of memory cells;
performing an erase-verify test for the plurality of memory cells; and
before the applying of the erase voltage, pre-charging the channel by applying a pre-charge voltage which is lower than the erase voltage to the one end of the active area, the pre-charge voltage charges the channel by gate-induced drain leakage of a select gate at the one end of the active area.
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Abstract
An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.
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Citations
23 Claims
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1. A method for performing an erase operation, comprising:
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charging a channel of an active area of a plurality of memory cells, the charging of the channel comprises applying an erase voltage to one end of the active area, the plurality of memory cells are formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the active area comprises a pillar which extends vertically in the three-dimensional non-volatile memory; during the charging of the channel, setting control gate voltages of the plurality of memory cells to encourage erasing of the memory cells, the setting the control gate voltages is based on an assignment of the plurality of memory cells to different groups, each group of the different groups comprises multiple adjacent memory cells of the plurality of memory cells; performing an erase-verify test for the plurality of memory cells; and before the applying of the erase voltage, pre-charging the channel by applying a pre-charge voltage which is lower than the erase voltage to the one end of the active area, the pre-charge voltage charges the channel by gate-induced drain leakage of a select gate at the one end of the active area. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 23)
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12. A non-volatile memory device, comprising:
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a substrate; a plurality of memory cells comprising an active area, the active area comprising a channel, the plurality of memory cells are formed above the substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the active area comprises a pillar which extends vertically in the three-dimensional non-volatile memory, the plurality of memory cells are subdivided into different groups based on group assignments, and each group of the different groups comprises multiple adjacent memory cells of the plurality of memory cells, wherein the active area is U-shaped and comprises two pillars which extend vertically in the three-dimensional non-volatile memory, and the groups extend from one end of the active area to a back gate of the active area; and circuitry coupled with the plurality of memory cells, the circuitry, to perform an erase operation for the plurality of memory cells is configured to;
apply an erase voltage to one end of the active area to charge the channel, during the charging of the channel, set control gate voltages of the plurality of memory cells to encourage erasing of the memory cells, and perform an erase-verify test for the plurality of memory cells, the setting the control gate voltages is based on the groups assignments. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A method for performing an erase operation, comprising:
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applying an erase voltage to one end of an active area of a plurality of memory cells, the plurality of memory cells are formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the active area comprises a pillar which extends vertically in the three-dimensional non-volatile memory, the plurality of memory cells are assigned to different groups, and each group comprises multiple adjacent memory cells of the plurality of memory cells; during the applying of the erase voltage, setting control gate voltages of the plurality of memory cells to encourage erasing of the memory cells, wherein the control gate voltages are common within each group; and performing an erase-verify test for the plurality of memory cells. - View Dependent Claims (19, 20, 21, 22)
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Specification