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Group word line erase and erase-verify methods for 3D non-volatile memory

  • US 9,047,973 B2
  • Filed: 05/09/2014
  • Issued: 06/02/2015
  • Est. Priority Date: 02/14/2013
  • Status: Active Grant
First Claim
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1. A method for performing an erase operation, comprising:

  • charging a channel of an active area of a plurality of memory cells, the charging of the channel comprises applying an erase voltage to one end of the active area, the plurality of memory cells are formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the active area comprises a pillar which extends vertically in the three-dimensional non-volatile memory;

    during the charging of the channel, setting control gate voltages of the plurality of memory cells to encourage erasing of the memory cells, the setting the control gate voltages is based on an assignment of the plurality of memory cells to different groups, each group of the different groups comprises multiple adjacent memory cells of the plurality of memory cells;

    performing an erase-verify test for the plurality of memory cells; and

    before the applying of the erase voltage, pre-charging the channel by applying a pre-charge voltage which is lower than the erase voltage to the one end of the active area, the pre-charge voltage charges the channel by gate-induced drain leakage of a select gate at the one end of the active area.

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