Combined signal delay and power saving for use with a plurality of memory circuits
First Claim
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1. A method comprising:
- receiving at an interface to a simulated memory device, a control signal sent to control the simulated memory device, where the simulated memory device differs in at least one aspect from a plurality of physical memory circuits;
identifying at least one portion of the physical memory circuits that is not currently being accessed, the physical memory circuits including at least one other portion that is currently being accessed; and
in response to identifying at least one portion of the physical memory circuits that is not being accessed, initiating a power saving operation in association with the identified at least one portion of the physical memory circuits, wherein the power saving operation includes delaying communication of the control signal from the interface to the identified at least one portion of the physical memory circuits to control the identified at least one portion of the physical memory circuits.
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Abstract
A system and method are provided. In use, at least one of a plurality of memory circuits is identified. In association with the at least one memory circuit, a power saving operation is performed and the communication of a signal thereto is delayed.
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Citations
24 Claims
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1. A method comprising:
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receiving at an interface to a simulated memory device, a control signal sent to control the simulated memory device, where the simulated memory device differs in at least one aspect from a plurality of physical memory circuits; identifying at least one portion of the physical memory circuits that is not currently being accessed, the physical memory circuits including at least one other portion that is currently being accessed; and in response to identifying at least one portion of the physical memory circuits that is not being accessed, initiating a power saving operation in association with the identified at least one portion of the physical memory circuits, wherein the power saving operation includes delaying communication of the control signal from the interface to the identified at least one portion of the physical memory circuits to control the identified at least one portion of the physical memory circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A memory apparatus comprising:
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a plurality of first memory circuits; and a component coupled in communication with the plurality of first memory circuits and operable to; simulate at least one second memory circuit different from the plurality of first memory circuits; receive a control signal sent to control the at least one second memory circuit; identify at least one of the first memory circuits that is not being accessed when the first memory circuits include at least one other first memory circuit that is being accessed; and initiate a power saving operation in association with the identified at least one first memory circuit, wherein the power saving operation includes delaying communication of the control signal to the identified at least one first memory circuit to control the identified at least one first memory circuit. - View Dependent Claims (24)
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Specification