Combined signal delay and power saving for use with a plurality of memory circuits

• US 9,047,976 B2
• Filed: 10/26/2006
• Issued: 06/02/2015
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Schakel, Keith R., Smith, Michael John Sebastian, Wang, David T., Weber, Frederick Daniel
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Chang, Eric
• Application Number:
  US11/553,390
• Publication Number:
  US 20080123459A1
• Time in Patent Office: 3,141 Days
• Field of Search: 713/320, 713/300
• US Class Current: 1/1
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A system and method are provided. In use, at least one of a plurality of memory circuits is identified. In association with the at least one memory circuit, a power saving operation is performed and the communication of a signal thereto is delayed.

Claims

1. A method comprising:

receiving at an interface to a simulated memory device, a control signal sent to control the simulated memory device, where the simulated memory device differs in at least one aspect from a plurality of physical memory circuits;

identifying at least one portion of the physical memory circuits that is not currently being accessed, the physical memory circuits including at least one other portion that is currently being accessed; and

in response to identifying at least one portion of the physical memory circuits that is not being accessed, initiating a power saving operation in association with the identified at least one portion of the physical memory circuits, wherein the power saving operation includes delaying communication of the control signal from the interface to the identified at least one portion of the physical memory circuits to control the identified at least one portion of the physical memory circuits.

2. The method of claim 1, wherein delaying communication of the control signal is for a fixed amount of time.

3. The method of claim 1, wherein delaying communication of the control signal is for a variable amount of time.

4. The method of claim 1, wherein the control signal is associated with an operation, wherein the operation includes at least one of:

a write operation;

a read operation;

a refresh operation;

a mode register write operation;

a mode register read operation;

an activate operation;

or

a precharge operation.

5. The method of claim 4, wherein delaying communication of the control signal includes delaying communication of the control signal for a fixed period of time.

6. The method of claim 4, wherein delaying communication of the control signal includes:

delaying communication of the control signal for a variable period of time.

7. The method of claim 1, wherein delaying communication of the control signal is performed as a function of the control signal.

8. The method of claim 1, wherein delaying communication of the control signal is performed as a function of a previous signal.

9. The method of claim 1, wherein identifying at least one portion includes determining whether the at least one portion is being accessed.

10. The method of claim 1, wherein the power saving operation further includes:

performing a power down operation.

11. The method of claim 10, wherein the power down operation includes performing a precharge power down operation.

12. The method of claim 1, wherein the power saving operation further includes de-asserting an enable input of at least one physical memory circuit that is not currently being accessed.

13. The method of claim 12, wherein de-asserting the enable input includes de-asserting a clock enable input of at least one physical memory circuit that is not currently being accessed.

14. The method of claim 1, wherein the control signal provides a command.

15. The method of claim 1, wherein the power saving operation includes minimizing a current draw.

16. The method of claim 1, wherein delaying communication of the control signal includes delaying communication of the control signal for a fraction of a clock cycle.

17. The method of claim 1, wherein delaying communication of the control signal includes delaying communication of the control signal for one or more clock cycles.

18. The method of claim 1, further comprising:

receiving, at the interface, a second signal sent to the simulated memory device,

wherein the control signal and second signal are associated with a same operation.

19. The method of claim 18, wherein the operation includes at least one of:

a write operation;

a read operation;

a refresh operation;

a mode register write operation;

a mode register read operation;

an activate operation;

or

a precharge operation.

20. The method of claim 18, wherein the second signal includes an address signal or a second control signal.

21. The method of claim 18, wherein the second signal includes a data signal.

22. The method of claim 1, further comprising:

receiving, at the interface, a plurality of second signals sent to the simulated memory device,

wherein the control signal and the plurality of second signals are associated with an operation, and where the plurality of second signals include a data signal and either an address signal or a control signal.

23. A memory apparatus comprising:

a plurality of first memory circuits; and

a component coupled in communication with the plurality of first memory circuits and operable to;

simulate at least one second memory circuit different from the plurality of first memory circuits;

receive a control signal sent to control the at least one second memory circuit;

identify at least one of the first memory circuits that is not being accessed when the first memory circuits include at least one other first memory circuit that is being accessed; and

initiate a power saving operation in association with the identified at least one first memory circuit, wherein the power saving operation includes delaying communication of the control signal to the identified at least one first memory circuit to control the identified at least one first memory circuit.

24. The memory apparatus of claim 23, wherein the power saving operation further includes a power down operation.