Temperature compensation of conductive bridge memory arrays

• US 9,047,983 B2
• Filed: 04/19/2014
• Issued: 06/02/2015
• Est. Priority Date: 01/20/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Samachisa, George
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US14/256,925
• Publication Number:
  US 20140226393A1
• Time in Patent Office: 409 Days
• Field of Search: 365/189.09, 365/185.18, 365/185.2, 365/185.28, 365/211
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/12 : Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/08 : Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

Claims

1. A method for operating a monolithic three-dimensional memory array, comprising:

acquiring a temperature associated with the monolithic three-dimensional memory array, the monolithic three-dimensional memory array includes a first storage element and a second storage element, the first storage element is located above the second storage element, the second storage element is located above a substrate, the monolithic three-dimensional memory array includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction perpendicular to the first direction, the plurality of word lines includes a selected word line and a plurality of unselected word lines, the plurality of bit lines includes a selected bit line and a plurality of unselected bit lines, the first storage element is in communication with the selected word line and the selected bit line, the monolithic three-dimensional memory array includes a plurality of unselected storage elements in communication with the plurality of unselected word lines and the plurality of unselected bit lines;

applying a first voltage difference across the plurality of unselected storage elements based on the temperature; and

setting the first storage element into a first state while performing the applying a first voltage difference across the plurality of unselected storage elements, the setting the first storage element into a first state includes applying a second voltage difference across the first storage element.

2. The method of claim 1, wherein:

the first storage element and the second storage element are arranged in a vertical column that is perpendicular to the substrate.

3. The method of claim 1, wherein:

the first storage element and the second storage element are in communication with the selected bit line, the selected bit line is arranged in a vertical direction that is perpendicular to the substrate.

4. The method of claim 1, wherein:

the applying a first voltage difference across the plurality of unselected storage elements includes applying one or more unselected word line voltages to the plurality of unselected word lines and applying one or more unselected bit line voltages to the plurality of unselected bit lines; and

the applying a second voltage difference across the first storage element includes applying a selected word line voltage to the selected word line and applying a selected bit line voltage to the selected bit line.

5. The method of claim 4, wherein:

the first state is associated with a programming state of the first storage element; and

the second voltage difference across the first storage element is associated with a programming voltage of the first storage element.

6. The method of claim 4, wherein:

the first state is associated with a reading state of the first storage element; and

the second voltage difference across the first storage element is associated with a reading voltage of the first storage element.

7. The method of claim 4, further comprising:

sensing the first storage element while applying the second voltage difference across the first storage element.

8. The method of claim 4, further comprising:

determining a particular number of write cycles associated with the monolithic three-dimensional memory array, the applying one or more unselected word line voltages to the plurality of unselected word lines includes generating the one or more unselected word line voltages based on the temperature and the particular number of write cycles.

9. The method of claim 8, wherein:

the determining a particular number of write cycles includes determining a number of write cycles that have occurred since a last erase of the monolithic three-dimensional memory array.

10. The method of claim 4, further comprising:

determining a particular number of write cycles associated with a page within the monolithic three-dimensional memory array, the page is associated with the selected word line, the applying one or more unselected word line voltages to the plurality of unselected word lines includes generating the one or more unselected word line voltages based on the temperature and the particular number of write cycles.

11. The method of claim 10, wherein:

the determining a particular number of write cycles includes determining a number of write cycles that have occurred since a last refresh of the page.

12. The method of claim 1, wherein:

the acquiring a temperature associated with the monolithic three-dimensional memory array includes sensing the temperature using a temperature sensor located on a die including the monolithic three-dimensional memory array.

13. A method for operating a three-dimensional memory array, comprising:

detecting a first condition associated with the three-dimensional memory array, the three-dimensional memory array includes a first layer of memory cells and a second layer of memory cells, the first layer of memory cells includes a first memory cell, the second layer of memory cells includes a second memory cell, the first memory cell is located above the second memory cell, the second memory cell is located above a substrate, the detecting a first condition includes at least one of detecting a temperature associated with the three-dimensional memory array or detecting a particular number of write cycles associated with the three-dimensional memory array, the three-dimensional memory array includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction, the plurality of word lines includes a selected word line and a plurality of unselected word lines, the plurality of bit lines includes a selected bit line and a plurality of unselected bit lines, the first memory cell is in communication with the selected word line and the selected bit line, the three-dimensional memory array includes a plurality of unselected memory cells in communication with the plurality of unselected word lines and the plurality of unselected bit lines;

applying a first voltage difference across the plurality of unselected memory cells based on the first condition;

applying a second voltage difference across the first memory cell while applying the first voltage difference across the plurality of unselected memory cells; and

sensing the first storage element while applying the second voltage difference across the first memory cell.

14. The method of claim 13, wherein:

the first memory cell and the second memory cell are arranged in a vertical column that is perpendicular to the substrate.

15. The method of claim 13, wherein:

the first memory cell and the second memory cell are in communication with the selected bit line, the selected bit line is arranged in a vertical direction that is perpendicular to the substrate.

16. The method of claim 13, wherein:

the applying a first voltage difference across the plurality of unselected memory cells includes applying one or more unselected word line voltages to the plurality of unselected word lines and applying one or more unselected bit line voltages to the plurality of unselected bit lines; and

the applying a second voltage difference across the first memory cell includes applying a selected word line voltage to the selected word line and applying a selected bit line voltage to the selected bit line.

17. The method of claim 13, further comprising:

determining the particular number of write cycles associated with the memory array based on a number of write cycles that have occurred since a last erase of the three-dimensional memory array, the applying one or more unselected word line voltages to the plurality of unselected word lines includes generating the one or more unselected word line voltages based on the temperature and the particular number of write cycles.

18. A non-volatile storage system, comprising:

a three-dimensional memory array, the three-dimensional memory array includes a first layer of storage elements and a second layer of storage elements, the first layer of storage elements includes a first storage element, the second layer of storage elements includes a second storage element, the first storage element is located above the second storage element, the second storage element is located above a substrate, the three-dimensional memory array includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction, the plurality of word lines includes a selected word line and a plurality of unselected word lines, the plurality of bit lines includes a selected bit line and a plurality of unselected bit lines, the first storage element is connected to the selected word line and the selected bit line, the three-dimensional memory array includes a plurality of unselected storage elements connected to the plurality of unselected word lines and the plurality of unselected bit lines; and

one or more managing circuits in communication with the plurality of word lines and the plurality of bit lines, the one or more managing circuits acquire a temperature associated with the three-dimensional memory array, the one or more managing circuits cause a first voltage difference to be applied across the plurality of unselected storage elements based on the temperature, the one or more managing circuits cause a second voltage difference to be applied across the first storage element while the first voltage difference is applied across the plurality of unselected storage elements, the one or more managing circuits cause the first storage element to be sensed while the second voltage difference is applied across the first storage element.

19. The non-volatile storage system of claim 18, wherein:

the first storage element and the second storage element are arranged in a vertical column that is perpendicular to the substrate.

20. The non-volatile storage system of claim 18, wherein:

the first storage element and the second storage element are connected to the selected bit line, the selected bit line is arranged in a vertical direction that is perpendicular to the substrate.

21. The non-volatile storage system of claim 18, wherein:

the first voltage difference is applied across the plurality of unselected storage elements by applying one or more unselected word line voltages to the plurality of unselected word lines and applying one or more unselected bit line voltages to the plurality of unselected bit lines; and

the second voltage difference is applied across the first storage element by applying a selected word line voltage to the selected word line and applying a selected bit line voltage to the selected bit line.

22. The non-volatile storage system of claim 18, wherein:

the one or more managing circuits determine a particular number of write cycles associated with the three-dimensional memory array based on a number of write cycles that have occurred since a last erase of the three-dimensional memory array, the one or more managing circuits cause the first voltage difference to be applied across the plurality of unselected storage elements based on the temperature and the particular number of write cycles.

23. The non-volatile storage system of claim 18, wherein:

the one or more managing circuits determine a particular number of write cycles associated with a page within the three-dimensional memory array, the page is associated with the selected word line, the one or more managing circuits cause the first voltage difference to be applied across the plurality of unselected storage elements based on the temperature and the particular number of write cycles.

24. The non-volatile storage system of claim 18, wherein:

the one or more managing circuits cause the first storage element to be sensed during a read operation of the first storage element.

25. The non-volatile storage system of claim 18, further comprising:

a temperature sensor, the temperature sensor determines the temperature associated with the three-dimensional memory array.