Semiconductor device with buried gates and method for fabricating the same

• US 9,048,218 B2
• Filed: 11/04/2010
• Issued: 06/02/2015
• Est. Priority Date: 03/31/2010
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Seung-Ryong, Ahn, Tae-Hang
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): SALERNO, SARAH KATE
• Application Number:
  US12/939,534
• Publication Number:
  US 20110241106A1
• Time in Patent Office: 1,671 Days
• Field of Search: 257/330, 257/E29.262, 257/E21.41, 438/270
• US Class Current: 1/1
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a supplementary layer and a silicon layer stacked over a substrate, a trench penetrating the supplementary layer and the silicon layer and formed over the substrate, a gate insulation layer formed along a surface of the trench, and a buried gate formed over the gate insulation layer and filling a portion of the trench.

Claims

1. A semiconductor device, comprising:

a supplementary layer formed over a substrate;

a silicon layer formed over the supplementary layer;

a trench penetrating the supplementary layer and the silicon layer and formed in the substrate;

a gate insulation layer formed along a surface of the trench;

a buried gate formed over the gate insulation layer and filling a portion of the trench; and

a junction region used as source region and drain region formed in the silicon layer and on both sides of the trench, wherein the junction region is spaced apart from the buried gate by at least a thickness of the supplementary layer,

wherein a top surface of the buried gate is disposed below a bottom surface of the supplementary layer.

2. The semiconductor device of claim 1, wherein the supplementary layer comprises a layer formed of one selected from the group consisting of silicon germanium (SiGe), silicon germanium carbide (SiGeC), and silicon carbide (SiC).

3. The semiconductor device of claim 1, wherein the supplementary layer comprises a layer formed of silicon germanium (SiGe), and germanium (Ge) content in the supplementary layer ranges from approximately 5% to approximately 30%.

4. The semiconductor device of claim 1, wherein the supplementary layer has a thickness ranging from approximately 50 Å

to approximately 500 Å

, and the silicon layer has a thickness ranging from approximately 100 Å

to approximately 500 Å

.

5. The semiconductor device of claim 1, further comprising:

a capping layer formed over the buried gate and filling a remaining portion of the trench.

6. The semiconductor device of claim 5, wherein the capping layer is not formed over the supplementary layer and the silicon layer.

7. The semiconductor device of claim 6, wherein the buried gate is spaced apart from the junction region by at least the supplementary layer.

18. The semiconductor device of claim 1, wherein the supplementary layer and the silicon layer is disposed on both sides of the trench, not inside the trench.

8. A method for fabricating a semiconductor device, comprising:

forming a supplementary layer over the substrate;

forming a silicon layer over the supplementary layer;

forming a junction region in the silicon layer;

forming a trench in the substrate by penetrating the silicon layer and the supplementary layer;

forming a gate insulation layer along a surface of the trench;

forming a buried gate filling a portion of the trench over the gate insulation layer,

wherein the junction region used as source region and drain region is spaced apart from the buried gate by at least a thickness of the supplementary layer,

wherein a top surface of the buried gate is disposed below a bottom surface of the supplementary layer.

9. The method of claim 8, wherein the supplementary layer comprises a layer formed of one selected from the group consisting of silicon germanium (SiGe), silicon germanium carbide (SiGeC), and silicon carbide (SiC).

10. The method of claim 8, wherein the supplementary layer comprises a layer formed of silicon germanium (SiGe), and germanium (Ge) content in the supplementary layer ranges from approximately 5% to approximately 30%.

11. The method of claim 8, wherein the supplementary layer and the silicon layer are formed in in-situ.

12. The method of claim 8, further comprising:

performing a pre-treatment process over the substrate before the supplementary layer and the silicon layer are stacked.

13. The method of claim 8, wherein the supplementary layer has a thickness ranging from approximately 50 Å

to approximately 500 Å

, and the silicon layer has a thickness ranging from approximately 100 Å

to approximately 500 Å

.

14. The method of claim 8, further comprising:

forming a capping layer filling a remaining portion of the trench over the buried gate.

15. The method of claim 8, wherein the supplementary layer and the silicon layer is disposed on both sides of the trench, not inside the trench.

16. The method of claim 8, wherein the junction region is formed in the silicon layer through an ion implantation.

17. The method of claim 14, wherein the capping layer is not formed over the supplementary layer and the silicon layer.