Package systems having interposers

• US 9,048,233 B2
• Filed: 05/26/2010
• Issued: 06/02/2015
• Est. Priority Date: 05/26/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Wei-Cheng, Hou, Shang-Yun, Jeng, Shin-Puu, Yu, Chen-Hua
• Primary Examiner(s): Menz, Laura
• Application Number:
  US12/787,661
• Publication Number:
  US 20110291288A1
• Time in Patent Office: 1,833 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05681 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/381 : Pitch distance

Abstract

A package system includes an integrated circuit disposed over an interposer. The interposer includes a first interconnect structure. A first substrate is disposed over the first interconnect structure. The first substrate includes at least one first through silicon via (TSV) structure therein. A molding compound material is disposed over the first interconnect structure and around the first substrate. The integrated circuit is electrically coupled with the at least one first TSV structure.

Claims

1. A package system comprising:

a first interposer comprising;

a first interconnect structure;

a first substrate disposed over the first interconnect structure, the first substrate comprising at least one first through silicon via (TSV) structure therein;

a molding compound material disposed over the first interconnect structure and around the first substrate, the molding compound material being free of direct contact with any first TSV structure formed therein; and

a second interconnect structure over the first substrate and having metallic lines and at least one dielectric layer; and

a first integrated circuit disposed over the first interposer, the first integrated circuit being electrically coupled with the at least one first TSV structure through the second interconnect structure and connecting bumps,

wherein

a top surface of the molding compound material is flush with a top surface of the second interconnect structure, and

a bottom surface of the molding compound material is flush with a bottom surface of the at least one first TSV structure.

2. The package system of claim 1, wherein the first integrated circuit comprises a second substrate, and a coefficient of thermal expansion (CTE) of the second substrate is substantially equal to a CTE of the first substrate.

3. The package system of claim 1, wherein a dimension of the first interconnect structure is larger than a dimension of the second interconnect structure.

4. The package system of claim 1, wherein the molding compound material further comprises:

at least one through via disposed outside the first substrate and surrounded by the molding compound material, wherein a portion of the second interconnect structure extends over at least a portion of the molding compound material and electrically couples with the at least one through via.

5. The package system of claim 1, further comprising:

a second integrated circuit disposed over the first interposer, wherein the second integrated circuit is electrically coupled with the at least one first TSV structure, the second integrated circuit comprises a third substrate, and a CTE of the third substrate is substantially equal to a CTE of the first substrate.

6. The package system of claim 1, further comprising:

a second interposer disposed between the first integrated circuit and the first interposer, wherein the second interposer comprises at least one third TSV structure, and the at least one third TSV structure is electrically coupled with the first integrated circuit and the at least one first TSV structure.

17. The package system of claim 1, wherein

the first interconnect structure comprises metallic lines having a first metallic line pitch, and

the second interconnect structure has a second metallic line pitch smaller than the first metallic line pitch.

18. The package system of claim 5, wherein the second integrated circuit is at least partially co-elevational with the first integrated circuit in a thickness direction of the first interposer.

7. A package system comprising:

a first interposer comprising;

a first interconnect structure, wherein the first interconnect structure has a first metallic line pitch;

a first substrate disposed over the first interconnect structure, the first substrate comprising at least one first through silicon via (TSV) structure therein;

a molding compound material disposed over the first interconnect structure and around the first substrate; and

a second, substantially planar interconnect structure disposed over the first substrate, wherein the second interconnect structure has a second metallic line pitch that is smaller than the first metallic line pitch; and

a first integrated circuit disposed over the first interposer, the first integrated circuit being electrically coupled with the at least one first TSV structure through the second interconnect structure and connecting bumps,

wherein the first interposer further comprises;

a molding compound layer between the first interconnect structure and the first substrate, wherein the at least one first TSV structure is disposed through the molding compound layer.

8. The package system of claim 7, wherein the first integrated circuit comprises a second substrate, and a coefficient of thermal expansion (CTE) of the second substrate is substantially equal to a CTE of the first substrate.

9. The package system of claim 7, wherein the molding compound material further comprises:

at least one through via disposed outside the first substrate and surrounded by the molding compound material, wherein a portion of the second interconnect structure extends over at least a portion of the molding compound material and electrically couples with the at least one through via.

10. The package system of claim 7, further comprising:

a second integrated circuit disposed over the first interposer, wherein the second integrated circuit is electrically coupled with the at least one first TSV structure, the second integrated circuit comprises a third substrate, and a CTE of the third substrate is substantially equal to a CTE of the first substrate.

11. The package system of claim 7, further comprising:

a second interposer disposed between the first integrated circuit and the first interposer, wherein the second interposer comprises at least one third TSV structure, and the at least one third TSV structure is electrically coupled with the first integrated circuit and the at least one first TSV structure.

12. A package system, comprising:

a first interposer comprising;

a first interconnect structure;

a first substrate disposed over the first interconnect structure, the first substrate comprising at least one first through silicon via (TSV) structure therein, wherein the first substrate has a first coefficient of thermal expansion (CTE);

a second, substantially planar interconnect structure disposed over the first substrate and having metallic lines and at least one dielectric layer; and

a molding compound material disposed over the first interconnect structure and surrounding the first substrate and the second interconnect structure; and

a first integrated circuit disposed over the first interposer, the first integrated circuit being electrically coupled with the at least one first TSV structure through the second interconnect structure and connecting bumps, wherein the first integrated circuit comprises a second substrate, the second substrate has a second CTE, and the second CTE is substantially equal to the first CTE,

wherein the first interposer further comprises;

a molding compound layer between the first interconnect structure and the first substrate, wherein the at least one first TSV structure is disposed through the molding compound layer.

13. The package system of claim 12, wherein a dimension of the first interconnect structure is larger than a dimension of the second interconnect structure.

14. The package system of claim 12, wherein the molding compound material further comprises:

at least one through via disposed in the molding compound material, wherein a portion of the second interconnect structure extends over at least a portion of the molding compound material and electrically couples with the at least one through via.

15. The package system of claim 12, further comprising:

a second integrated circuit disposed over the first interposer, wherein the second integrated circuit is electrically coupled with the at least one first TSV structure, the second integrated circuit comprises a third substrate, and a CTE of the third substrate is substantially equal to a CTE of the first substrate.

16. The package system of claim 12, further comprising:

a second interposer disposed between the first integrated circuit and the first interposer, wherein the second interposer comprises at least one third TSV structure, and the at least one third TSV structure is electrically coupled with the first integrated circuit and the at least one first TSV structure.

19. The package system of claim 12, wherein a top surface of the molding compound material is flush with a top surface of the second interconnect structure.