Off-chip vias in stacked chips

• US 9,048,234 B2
• Filed: 06/11/2013
• Issued: 06/02/2015
• Est. Priority Date: 10/10/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Mohammed, Ilyas, Oganesian, Vage, Ovrutsky, David, Mirkarimi, Laura Wills
• Primary Examiner(s): Tornow, Mark
• Assistant Examiner(s): BOYLE, ABBIGALE A
• Application Number:
  US13/914,896
• Publication Number:
  US 20130273693A1
• Time in Patent Office: 721 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/5382 : Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Claims

1. A method of fabricating a stacked microelectronic unit comprising:

a) forming a structure including a first microelectronic element having a front face facing a carrier, said first microelectronic element having a first edge extending away from said front face and a first trace extending along said front face towards said first edge;

b) removing material from said first edge until at least a portion of said first trace is exposed, said removing of material from said first edge forming an exposed portion of said first trace;

c) aligning and joining a second microelectronic element with said structure such that a front face of said second microelectronic element overlies a rear face opposite said front face of said first microelectronic element, said second microelectronic element having a second edge and a second trace extending along said front face of said second microelectronic element towards said second edge;

d) removing material from said second edge until at least a portion of said second trace is exposed, said removing of material from said second edge forming an exposed portion of said second trace;

e) before step c), forming at least one dielectric layer directly onto said rear face of said first microelectronic element and at least a portion of the exposed portion of said first trace; and

f) connecting a lead to at least one of said first and second traces, said lead extending along said at least one dielectric layer.

2. The method of claim 1, wherein said second microelectronic element includes a rear face opposite said front face, wherein said first edge extends between said front face and said rear face of said first microelectronic element, and wherein said second edge extends between said front face and said rear face of said second microelectronic element.

3. The method of claim 1, further comprising:

connecting a lead to each of said first and second traces.

4. The method of claim 1, further comprising:

thinning said structure including said first microelectronic element to form said rear face thereof.

5. The method of claim 1, wherein step c) of aligning and joining said second microelectronic element with said structure comprises positioning said second microelectronic element such that said second edge of said second microelectronic element is substantially aligned with said first edge of said first microelectronic element.

6. The method of claim 1, wherein step c) of aligning and joining said second microelectronic element with said structure comprises positioning said second microelectronic element such that said second edge of said second microelectronic element is laterally offset from said first edge of said first microelectronic element.

7. The method of claim 1, wherein said lead extends to said rear face of said second microelectronic element, further comprising:

forming a solder bump on said lead at a position adjacent to said rear face of said second microelectronic element.

8. The method of claim 1, wherein each of said first and second microelectronic elements includes a flash memory.

9. The method of claim 1, wherein said first microelectronic element is bonded to said carrier by an adhesive, and wherein said lead extends along at least a portion of said adhesive.

10. The method of claim 1, wherein said forming of at least said structure is performed with said first microelectronic element in a form of a reconstituted wafer.

11. The method of claim 1, wherein at least one of said removing of said material from said first edge of said first microelectronic element and said removing of said material from said second edge of said second microelectronic element is performed by using an etchant.

12. The method of claim 1, wherein said connecting said lead comprises depositing a metal so as to contact at least one of said traces, said lead extending along a surface of said at least one dielectric layer.

13. The method of claim 3, wherein said connecting said lead comprises depositing a metal so as to contact each of said traces, said lead extending along a surface of said at least one dielectric layer.

14. The method of claim 1, wherein when said second microelectronic element is joined with said structure and said dielectric layer is formed directly onto said rear face of said first microelectronic element, said second microelectronic element is joined directly onto a portion of said dielectric layer.

15. The method of claim 1, further comprising:

before step f), removing a portion of said formed dielectric layer to leave a remaining portion of said formed dielectric layer, said lead thereby being connected to extend along said remaining portion of said formed dielectric layer.