Apparatus and method for power MOS transistor
First Claim
Patent Images
1. A method comprising:
- providing a semiconductor device comprising;
a first trench comprising;
a dielectric layer formed in a lower portion of the first trench; and
a first gate region formed in an upper portion of the first trench;
a first N+ region and a second N+ region on opposite sides of the first trench; and
a second trench adjacent to the second N+ region, wherein a gate electrode material is filled in the second trench; and
forming accumulation layer along a sidewall of the second trench.
0 Assignments
0 Petitions
Accused Products
Abstract
A method comprises forming a first trench and a second trench, depositing a dielectric material in a lower portion of the first trench, depositing a gate electrode material in the second trench and an upper portion of the first trench, forming a first N+ region and a second N+ region through an ion implantation process, wherein the first N+ region and the second N+ region are on opposite sides of the first trench and forming an accumulation layer along a sidewall of the second trench.
-
Citations
20 Claims
-
1. A method comprising:
-
providing a semiconductor device comprising; a first trench comprising; a dielectric layer formed in a lower portion of the first trench; and a first gate region formed in an upper portion of the first trench; a first N+ region and a second N+ region on opposite sides of the first trench; and a second trench adjacent to the second N+ region, wherein a gate electrode material is filled in the second trench; and forming accumulation layer along a sidewall of the second trench. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method comprising:
-
forming a first trench and a second trench; depositing a dielectric material in a lower portion of the first trench; depositing a gate electrode material in the second trench and an upper portion of the first trench; forming a first N+ region and a second N+ region through an ion implantation process, wherein the first N+ region and the second N+ region are on opposite sides of the first trench; and forming an accumulation layer along a sidewall of the second trench. - View Dependent Claims (12, 13, 14, 15)
-
-
16. A method comprising:
-
forming a buried layer over a substrate; growing an epitaxial layer over the buried layer; forming a first trench and a second trench in the epitaxial layer and the buried layer, wherein; a width of the second trench is greater than a width of the first trench; forming a dielectric layer in a lower portion of the first trench; depositing a gate electrode material in the second trench and an upper portion of the first trench; and forming an accumulation layer along a sidewall of the second trench. - View Dependent Claims (17, 18, 19, 20)
-
Specification