Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies

• US 9,048,300 B2
• Filed: 12/17/2012
• Issued: 06/02/2015
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Chen, John, Yang, Simon
• Primary Examiner(s): CHEN, JACK S J
• Application Number:
  US13/716,533
• Publication Number:
  US 20130109142A1
• Time in Patent Office: 897 Days
• Field of Search: 438/199
• US Class Current: 1/1
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method for forming a CMOS integrated circuit device, the method including; providing a semiconductor substrate, forming a gate layer overlying the semiconductor substrate, patterning the gate layer to form NMOS and PMOS gate structures including edges; forming a first dielectric layer overlying the NMOS and PMOS gate structures to protect the NMOS and PMOS gate structures including the edges, forming a first masking layer overlying a first region adjacent the NMOS gate structure; etching a first source region and a first drain region adjacent to the PMOS gate structure using the first masking layer as a protective layer for the first region adjacent the NMOS gate structure, and depositing a silicon germanium material into the first source and drain regions to cause the channel region between the first source and drain regions of the PMOS gate structure to be strained in a compressive mode.

Claims

1. A method for forming a CMOS integrated circuit device, the method comprising:

providing a semiconductor substrate;

forming a gate layer overlying the semiconductor substrate;

patterning the gate layer to form an NMOS gate structure including edges and a PMOS gate structure including edges;

forming a first dielectric layer overlying the NMOS gate structure to protect the NMOS gate structure including the edges and overlying the PMOS gate structure to protect the PMOS gate structure including the edges;

forming a first masking layer overlying a first region adjacent the NMOS gate structure;

etching a first source region and a first drain region adjacent to the PMOS gate structure using the first masking layer as a protective layer for the first region adjacent the NMOS gate structure; and

depositing a silicon germanium material into the first source region and the first drain region to cause the channel region between the first source region and the first drain region of the PMOS gate structure to be strained in a compressive mode;

forming a second dielectric layer after depositing the silicon germanium material, the second dielectric layer overlying the NMOS gate structure and the PMOS gate structure to protect the deposited silicon germanium material, the PMOS gate structure including the edges, and the NMOS gate structure including the edges;

forming a second masking layer overlying a second region adjacent the PMOS gate structure;

etching a second source region and a second drain region adjacent to the NMOS gate structure using the second masking layer as a protective layer for the second region adjacent the PMOS gate structure; and

depositing silicon carbide material into the second source region and the second drain region to cause a channel region between the second source region and the second drain region of the NMOS gate structure to be strained in a tensile mode.

2. The method of claim 1 wherein the compressive mode increases a hole mobility.

3. The method of claim 1 wherein the channel region of the PMOS device has a length of 90 nanometers and less.

4. The method of claim 1 wherein the channel region of the NMOS device has a length of 90 nanometers and less.

5. The method of claim 1 wherein the silicon germanium material is an epitaxial material.

6. The method of claim 1 wherein the silicon germanium material has a thickness ranging from about 200 Angstroms to 1000 Angstroms.

7. The method of claim 1 wherein the depositing the silicon germanium material is an in-situ doped process using a boron species, the boron species having a concentration ranging from about 10¹⁹ to 10²⁰ atoms/cm³.

8. The method of claim 1 further comprising:

forming sidewall spacers on the edges of the NMOS gate structure after depositing the silicon germanium material; and

forming the second source region and the second drain region adjacent to the NMOS gate structure.

9. The method of claim 1 wherein the tensile mode increases an electron mobility.

10. The method of claim 1 wherein the silicon carbide material is an epitaxial material.

11. The method of claim 1 wherein the silicon carbide material has a thickness ranging from about 200 Angstroms to 1000 Angstroms.

12. The method of claim 1 wherein the depositing the silicon carbide material is an in-situ doped process using a phosphorus species, the phosphorus species having a concentration ranging from about 10¹⁹ to 10²⁰ atoms/cm³.

13. The method of claim 1 further comprising forming a refractory metal layer overlying the first source region and first drain region and the second source region and the second drain region.

14. The method of claim 1 wherein the first source region is an elevated first source region and the first drain region is an elevated first drain region, and the second source region is an elevated second source region and the second drain region is an elevated second drain region.

15. The method of claim 1 further comprising forming sidewall spacers on the edges of the NMOS gate structure after forming the second masking layer.

16. The method of claim 1 further comprising forming a third dielectric layer overlying the NMOS gate structure to cause a channel region between the second source region and the second drain region adjacent to the NMOS gate structure to be strained in a tensile mode.

17. The method of claim 16 wherein the third dielectric layer is silicon nitride deposited with tensile strain.