Field effect transistor with narrow bandgap source and drain regions and method of fabrication

• US 9,048,314 B2
• Filed: 08/21/2014
• Issued: 06/02/2015
• Est. Priority Date: 02/23/2005
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Datta, Suman, Kavalieros, Jack, Brask, Justin K., Doczy, Mark L., Metz, Matthew
• Primary Examiner(s): VALENTINE, JAMI M
• Application Number:
  US14/465,636
• Publication Number:
  US 20140361363A1
• Time in Patent Office: 285 Days
• Field of Search: 257/192, 257/366, 257/401, 438/471
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te

Abstract

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Claims

1. A transistor comprising:

a gate dielectric layer formed on a substrate;

a gate electrode formed on the gate dielectric layer; and

a pair of source/drain regions on opposite sides of the gate electrode, the pair of source/drain regions comprising a doped semiconductor film that extends beneath the gate electrode and above a top surface of the gate dielectric layer, wherein the semiconductor film comprises a material selected from the group consisting of InSb, InAs, and InP; and

wherein the semiconductor film is doped to an n-type conductivity with a silicon (Si), a tellurium (Te), or a sulfur (S) dopant.

2. The transistor of claim 1, wherein the semiconductor film comprises InAs.

3. The transistor of claim 1, further comprising a pair of non-alloyed metal contacts directly on the semiconductor film on opposite sides of the gate electrode.

4. The transistor of claim 1, wherein the semiconductor film is formed in a pair of recesses in the substrate on opposite sides of the gate electrode.

5. The transistor of claim 1, wherein the substrate comprises a buried oxide layer.

6. The transistor of claim 5, wherein the buried oxide layer has a thickness between 200-2,000 angstroms.

7. The transistor of claim 1, wherein the semiconductor film is doped with a concentration level between 1×

10¹⁶-1×

10¹⁹ atoms/cm³ of the Si dopant.

8. The transistor of claim 1, wherein the gate dielectric layer is formed of a dielectric selected from the group consisting of tantalum pentaoxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, lead zirconium titanate (PZT), and barium strontium titanate (BST).

9. A transistor comprising:

a substrate comprising a body having a top surface opposite a bottom surface and a pair of sidewalls;

a gate dielectric layer on the body along the top surface and the pair of sidewalls of the body;

a gate electrode on the gate dielectric layer along the top surface and the pair of sidewalls of the body; and

a pair of non-planar source/drain regions on the body on opposite sides of the gate electrode, the pair of non-planar source/drain regions comprising an in situ doped semiconductor film comprising a material selected from the group consisting of InSb, InAs, and InP that extends beneath the gate electrode, wherein the semiconductor film is doped to an n-type conductivity with a silicon (Si) dopant.

10. The transistor of claim 9, wherein the semiconductor film comprises InAs.

11. The transistor of claim 9, further comprising a pair of non-alloyed metal contacts directly on the semiconductor film on opposite sides of the gate electrode.

12. The transistor of claim 9, wherein the semiconductor film extends above a top surface of the gate dielectric layer.

13. The transistor of claim 9, wherein the substrate comprises a buried oxide layer.

14. The transistor of claim 9, wherein the semiconductor film is formed in a pair of recesses in the body on opposite sides of the gate electrode.

15. The transistor of claim 9, wherein the body is on the buried oxide layer.

16. The transistor of claim 15, wherein the buried oxide layer has a thickness between 200-2,000 angstroms.

17. The transistor of claim 9, wherein the semiconductor film is doped with a concentration level between 1×

10¹⁶-1×

10¹⁹ atoms/cm³ of the Si dopant.

18. The transistor of claim 9, wherein the gate dielectric layer is formed of a dielectric selected from the group consisting of tantalum pentaoxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, lead zirconium titanate (PZT), and barium strontium titanate (BST).