Display device having an oxide semiconductor transistor
First Claim
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1. A display device comprising:
- a first scan line and a second scan line;
a first insulating layer over the first scan line and the second scan line;
an oxide semiconductor layer over the first insulating layer;
a signal line over the oxide semiconductor layer; and
a second insulating layer over the signal line,wherein the signal line intersects the first scan line and the second scan line at a first intersection and a second intersection, respectively,wherein the signal line comprises a first convex and a second convex at the first intersection and the second intersection, respectively,wherein the signal line is substantially entirely flat in a region between the first convex and the second convex,wherein the oxide semiconductor layer is located at the first intersection, andwherein the signal line is entirely in contact with the first insulating layer in the region.
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Abstract
An object is to reduce parasitic capacitance of a signal line included in a liquid crystal display device. A transistor including an oxide semiconductor layer is used as a transistor provided in each pixel. Note that the oxide semiconductor layer is an oxide semiconductor layer which is highly purified by thoroughly removing impurities (hydrogen, water, or the like) which become electron suppliers (donors). Thus, the amount of leakage current (off-state current) can be reduced when the transistor is off. Therefore, a voltage applied to a liquid crystal element can be held without providing a capacitor in each pixel. In addition, a capacitor wiring extending to a pixel portion of the liquid crystal display device can be eliminated. Therefore, parasitic capacitance in a region where the signal line and the capacitor wiring intersect with each other can be eliminated.
156 Citations
15 Claims
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1. A display device comprising:
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a first scan line and a second scan line; a first insulating layer over the first scan line and the second scan line; an oxide semiconductor layer over the first insulating layer; a signal line over the oxide semiconductor layer; and a second insulating layer over the signal line, wherein the signal line intersects the first scan line and the second scan line at a first intersection and a second intersection, respectively, wherein the signal line comprises a first convex and a second convex at the first intersection and the second intersection, respectively, wherein the signal line is substantially entirely flat in a region between the first convex and the second convex, wherein the oxide semiconductor layer is located at the first intersection, and wherein the signal line is entirely in contact with the first insulating layer in the region. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A display device comprising:
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a first scan line and a second scan line; a first insulating layer over the first scan line and the second scan line; a first signal line and a second signal line over the first insulating layer; a transistor surrounded by the first scan line, the second scan line, the first signal line, and the second signal line, the transistor comprising a gate, the first insulating layer over the gate, and an oxide semiconductor layer over the first insulating layer; a second insulating layer over the first signal line and the second signal line; and a pixel electrode over the second insulating layer, wherein the first signal line intersects the first scan line and the second scan line at a first intersection and a second intersection, respectively, wherein the first signal line comprises a first convex and a second convex at the first intersection and the second intersection, respectively, wherein the first signal line is substantially entirely flat in a region between the first convex and the second convex, wherein the oxide semiconductor layer is located at the first intersection, wherein the first signal line is entirely in contact with the first insulating layer in the region, and wherein the pixel electrode is electrically connected to the transistor through a contact hole located in the second insulating layer. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsKondo, Toshikazu, Koyama, Jun, Yamazaki, Shunpei
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Primary Examiner(s)Wright, Tucker
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Application NumberUS13/944,996Publication NumberTime in Patent Office684 DaysField of Search257/59, 257/43, 257/E33.053US Class Current1/1CPC Class CodesG02F 1/133345 Insulating layers G02F1/133...G02F 1/13606 having means for reducing p...G02F 1/136227 Through-hole connection of ...G02F 1/13624 having more than one switch...G02F 1/136286 Wiring, e.g. gate line, dra...G02F 1/136295 Materials; Compositions; Ma...G02F 1/1368 in which the switching elem...G02F 2202/10 semiconductorG09G 2300/0426 Layout of electrodes and co...G09G 3/3622 using a passive matrix G09G...H01L 27/1225 with semiconductor material...H01L 27/1244 for preventing breakage, pe...H01L 29/45 Ohmic electrodesH01L 29/7869 having a semiconductor body...
