Integrated circuit capacitor and method

• US 9,048,341 B2
• Filed: 04/19/2012
• Issued: 06/02/2015
• Est. Priority Date: 03/16/2011
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Shih-Hung, Hsieh, Kuang-Yeu
• Primary Examiner(s): FERNANDES, ERROL V
• Application Number:
  US13/451,428
• Publication Number:
  US 20130277799A1
• Time in Patent Office: 1,139 Days
• Field of Search: 257/295, 257/306, 257/532, 257/758, 438/3, 438/253, 438/255, 438/26, 438/382, 438/396, 438/618, 438/386
• US Class Current: 1/1
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers

Abstract

An example of a capacitor includes a series of ridges and trenches and an interconnect region on the integrated circuit substrate. The series of ridges and trenches and the interconnect region have a capacitor foundation surface with a serpentine cross-sectional shape on the series of ridges and trenches. Electrical conductors are electrically connected to the electrode layers from the interconnect region for access to the electrode layers of the capacitor assembly.

Claims

1. A capacitor comprising:

a substrate having a capacitor region and an interconnect region;

a series of ridges and trenches at the capacitor region;

the interconnect region located laterally from the capacitor region;

the interconnect region and the capacitor region having a capacitor foundation surface;

the capacitor foundation surface having a serpentine cross-sectional shape on the series of ridges and trenches at the capacitor region;

a serpentine, stacked plate capacitor assembly, comprising at least two electrically conductive electrode layers and dielectric layers separating the electrode layers, at the capacitor foundation surface of the capacitor region, the serpentine, stacked plate capacitor assembly creating a stack of one or more capacitors; and

electrical conductors at the interconnect region electrically connected to the electrode layers for access to the electrode layers of the capacitor assembly.

2. The capacitor according to claim 1, wherein the capacitor foundation surface is electrically conductive and constitutes an electrode layer.

3. The capacitor according to claim 1, wherein the interconnect region in spaced apart from the series of ridges and trenches.

4. The capacitor according to claim 1, wherein the electrical conductors pass through vertical vias in the interconnect region, the vertical vias overlying landing pads of the electrode layers, the electrical conductors electrically connected to the landing pads.

5. The capacitor according to claim 4, wherein each electrical conductor is electrically connected to one landing pad of one electrode layer.

6. The capacitor according to claim 4, wherein the landing pads to which the electrical conductors are electrically connected are arranged in a stair stepped arrangement.

7. The capacitor according to claim 1, wherein the series of ridges are located above and extend away from the substrate.

8. The capacitor according to claim 1, wherein some but not all of the capacitors are connected in parallel.

9. The capacitor according to claim 1, wherein:

the ridges have ridge widths, the trenches have trenches widths, the ridge widths and the trench widths extending in a first direction;

the ridges have ridge heights extending in a second direction, the second direction being perpendicular to the first direction;

the ridges have ridge lengths measured in a third direction, the third direction being perpendicular to the first and second directions;

the ridges have sidewall surfaces extending in the second and third directions;

the ridges have top wall surfaces extending in the first and third direction; and

the substrate comprises a substrate surface extending in the first and third direction.

10. A capacitor comprising:

a substrate having a capacitor region and an interconnect region;

a series of ridges and trenches at the capacitor region;

the interconnect region located laterally from the capacitor region;

the interconnect region and the capacitor region having a capacitor foundation surface;

the capacitor foundation surface having a serpentine cross-sectional shape on the series of ridges and trenches at the capacitor region;

a serpentine, stacked plate capacitor assembly, comprising at least two electrically conductive electrode layers and dielectric layers separating the electrode layers, at the capacitor foundation surface of the capacitor region, the serpentine, stacked plate capacitor assembly creating a stack of one or more capacitors;

the interconnect region having landing pads;

electrical conductors contacting the landing pads at the interconnect region electrically connected to the electrode layers for access to the electrode layers of the capacitor assembly; and

at least an additional one of the ridges or trenches constituting the interconnect region with the landing pads being located as follows;

when the additional one is an additional trench, the landing pads are located at the bottom of the additional trench; and

when the additional one is an additional ridge, the landing pads are located at the top of the additional ridge.

11. A capacitor comprising:

a substrate having a first trench, a capacitor region located within the first trench, and an interconnect region;

a series of ridges located within the first trench at the capacitor region, the ridges separated by second trenches;

the interconnect region located laterally from the capacitor region;

the interconnect region and the capacitor region having a capacitor foundation surface;

the capacitor foundation surface having a serpentine cross-sectional shape on the series of ridges and second trenches at the capacitor region within the first trench;

a serpentine, stacked plate capacitor assembly, comprising at least two electrically conductive electrode layers and dielectric layers separating the electrode layers, at the capacitor foundation surface of the capacitor region, the serpentine, stacked plate capacitor assembly creating a stack of one or more capacitors; and

electrical conductors at the interconnect region electrically connected to the electrode layers for access to the electrode layers of the capacitor assembly.