Switched-mode power supply startup circuit, method, and system incorporating same

• US 9,048,747 B2
• Filed: 11/20/2012
• Issued: 06/02/2015
• Est. Priority Date: 11/23/2011
• Status: Expired due to Fees

• Current Assignee: Zahid Ansari
• Original Assignee: Zahid Ansari
• Inventors: Ansari, Zahid
• Primary Examiner(s): Dole, Timothy J
• Assistant Examiner(s): AHMED, YUSEF A
• Application Number:
  US13/682,554
• Publication Number:
  US 20130127431A1
• Time in Patent Office: 924 Days
• Field of Search: 363 49- 50, 363 2101- 2118, 363/16, 323222-225, 323271-275, 323282-285
• US Class Current: 1/1
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 1/0048 Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H02M 3/335 using semiconductor devices only
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A startup circuit delivers regulated startup current to a control IC in a switched-mode power supply (SMPS) system, and automatically disconnects the startup current when the SMPS Control IC starts switching the transformer or inductor used as the energy storage element in the SMPS system. Disconnection of the startup current may be triggered by detecting a time-varying voltage waveform on an accessible node in the SMPS system, or by detecting an increased current consumption by the SMPS Control IC, without requiring any ground reference to the SMPS Control IC, nor without requiring any logic signals generated by the SMPS Control IC. This provides for rapid and predictable startup of an SMPS Control IC and reduced power loss once the SMPS Control IC is operational, and is independent of the operating voltages of the SMPS control IC, and independent of the particular control scheme and switch topology of the SMPS system.

Claims

1. A startup circuit for a switched-mode power supply, said startup circuit comprising:

a voltage input node;

an output current node;

a disable input node;

a startup current circuit configured to provide a startup current from the voltage input node to the output current node when enabled, and to block the startup current when disabled, said startup current being substantially constant in magnitude irrespective of a voltage difference between the voltage input node and the output current node; and

a control circuit configured to enable the startup current circuit when a voltage is first applied to the voltage input node, and to disable the startup current circuit in response to one or more voltage excursions on the disable input node which exceed by a first offset a voltage of the output current node;

wherein said control circuit comprises;

a first power supply node coupled to a first node of the startup current circuit;

a reference power supply node coupled to the output current node;

an input circuit having an input coupled to the disable input node, said input circuit configured to generate on an output node thereof a signal having different voltage and time characteristics relative to a signal coupled to its input node; and

a comparator circuit having a first input coupled to the input circuit output node, having a second input coupled to the output current node, and having an output coupled to an enable input for the startup current circuit, said comparator circuit configured to disable the startup current circuit when a voltage of the first input exceeds a voltage of the second input by a second offset.

2. The startup circuit as recited in claim 1 wherein:

the control circuit draws a standby current that is less than 1% of the startup current irrespective of the voltage difference between the voltage input node and the output current node.

3. The startup circuit as recited in claim 1 wherein:

the first offset is within the range of 10-500 mV.

4. The startup circuit as recited in claim 1 wherein:

the first offset is within the range of 200-500 mV.

5. The startup circuit as recited in claim 1 wherein the startup current circuit comprises:

a normally-on transistor coupled between the voltage input node and the first node, having a control terminal coupled to the output current node;

a resistor coupled between the first node and a second node; and

a transistor switch device coupled between the second node and the output current node, having a control terminal coupled to an output node of the control circuit.

6. The startup circuit as recited in claim 5 wherein the startup circuit is implemented on a monolithic integrated circuit.

7. The startup circuit as recited in claim 6 wherein the monolithic integrated circuit is capable of operating with a voltage difference as high as 373 volts between the voltage input node and the output current node.

8. The startup circuit as recited in claim 6 wherein:

the normally-on transistor comprises a junction field effect transistor (JFET); and

the transistor switch device comprises an insulated gate field effect transistor (IGFET).

9. The startup circuit as recited in claim 8 wherein

said input circuit is configured to generate on its output node an asymmetric signal relative to the signal coupled to its input node.

10. The startup circuit as recited in claim 9 wherein the monolithic integrated circuit is capable of operating with a voltage difference as high as 373 volts between the voltage input node and the output current node.

11. The startup circuit as recited in claim 10 wherein the monolithic integrated circuit is encapsulated using a low ionic content plastic compound to form a package that can tolerate steady-state power dissipation resulting from the startup current continuously flowing between the voltage input node and the output current node with a voltage difference as high as 373 volts between the voltage input node and the output current node.

12. The startup circuit as recited in claim 1 wherein said input circuit is configured to generate on its output node an asymmetric signal relative to the signal coupled to its input node.

13. The startup circuit as recited in claim 1 wherein:

the control circuit further comprises a latch circuit configured so that the startup current circuit, once disabled by the comparator circuit, remains disabled even in an absence of voltage excursions on the disable input node.

14. The startup circuit as recited in claim 1 wherein:

the second offset is within the range of 10-500 mV.

15. The startup circuit as recited in claim 14 wherein the first offset and the second offset are different in magnitude.

16. A computer-readable non-transitory storage medium including data structures encoding information useful for design, simulation, test, or fabrication of the startup circuit recited in claim 1.

17. The startup circuit as recited in claim 1 wherein the control circuit further comprises an offset voltage reference circuit coupled between the output current node and the second input of the comparator circuit.

18. The startup circuit as recited in claim 1 further comprising a power-coupling circuit path between the disable input node and the first power supply node of the control circuit.

19. A switched-mode power supply (SMPS) circuit comprising:

a startup circuit having a voltage input node, an output current node, and a disable input node, said startup circuit comprising;

a startup current circuit configured to provide a startup current from the voltage input node to the output current node when enabled, and to block the startup current when disabled, said startup current being substantially constant in magnitude irrespective of a voltage difference between the voltage input node and the output current node; and

a control circuit configured to enable the startup current circuit when a voltage is first applied to the voltage input node, and to disable the startup current circuit in response to one or more voltage excursions on the disable input node which exceed by a first offset a voltage of the output current node;

wherein said control circuit comprises;

a first power supply node coupled to a first node of the startup current circuit;

a reference power supply node coupled to the output current node;

an input circuit having an input coupled to the disable input node, said input circuit configured to generate on an output node thereof a signal having different voltage and time characteristics relative to a signal coupled to its input node; and

a comparator circuit having a first input coupled to the input circuit output node, having a second input coupled to the output current node, and having an output coupled to an enable input for the startup current circuit, said comparator circuit configured to disable the startup current circuit when a voltage of the first input exceeds a voltage of the second input by a second offset;

said SMPS circuit further comprising;

a switched-mode control circuit having a power supply terminal coupled to the output current node, having a ground terminal, and being configured when operational to pulse current through a coil of an energy storage transformer or inductor of the SMPS circuit; and

means for generating voltage excursions on the disable input node in response to said current pulses through said coil.

20. The switched-mode power supply circuit as recited in claim 19 wherein:

the startup circuit is implemented on a monolithic integrated circuit; and

the first offset is determined by one or more external components coupled to the monolithic integrated circuit.

21. The switched-mode power supply circuit as recited in claim 19 wherein the means for generating comprises:

a coupling capacitor disposed between the disable input node and another node that exhibits a time-varying voltage waveform when the switched-mode control circuit is operational.

22. The switched-mode power supply circuit as recited in claim 19 wherein the means for generating comprises:

a direct connection from the disable input node to another node that exhibits a time-varying voltage waveform having voltage excursions that exceed the voltage of the output current node when the switched-mode control circuit is operational.

23. A method for starting up a switched-mode power supply (SMPS) circuit, said method comprising:

providing a startup current to a power supply terminal of a switched-mode control circuit to thereby develop an increasing voltage on the power supply terminal, said startup current being substantially constant in magnitude irrespective of the magnitude of an input voltage provided to the SMPS circuit;

generating on a disable node a voltage excursion exceeding by a first offset the voltage of the power supply terminal when the switched-mode control circuit begins to operate; and

disabling the startup current provided to the power supply terminal in response to the voltage excursion on the disable node, said disabling comprising;

generating an output signal on an input circuit output node, said input circuit having an input node coupled to the disable node, said output signal having different voltage and time characteristics relative to a signal coupled to its input node;

generating an output signal on an output of a comparator circuit, said comparator circuit having a first input coupled to the input circuit output node, having a second input coupled to the power supply terminal, and having said output coupled to an enable input for a startup current circuit, said output signal being suitable to disable the startup current circuit when a voltage of the first comparator input exceeds a voltage of the second comparator input by a second offset.

24. The method as recited in claim 23 further comprising:

re-enabling the startup current provided to the power supply terminal upon an absence, for a first duration, of a voltage excursion on the disable node.

25. The method as recited in claim 23 wherein:

the first offset is within the range of 10-500 mV.

26. The method as recited in claim 23 further comprising:

generating a respective voltage excursion on the disable node for each respective current pulse through a coil of an energy storage transformer or inductor of the SMPS circuit, each respective voltage excursion exceeding by the first offset the voltage of the power supply terminal.

27. The method as recited in claim 23 wherein:

the voltage excursion on the disable node constantly exceeds by the first offset the voltage of the power supply terminal so long as the switched-mode control circuit continues to operate.

28. A method for making a startup circuit product for a switched-mode power supply, said method comprising:

providing a voltage input node;

providing an output current node;

providing a disable input node;

providing a startup current circuit configured to provide a startup current from the voltage input node to the output current node when enabled, and to block the startup current when disabled, said startup current being substantially constant in magnitude irrespective of the voltage difference between the voltage input node and the output current node; and

providing a control circuit configured to enable the startup current circuit when a voltage is first applied to the voltage input node, and to disable the startup current circuit after a voltage conveyed to the disable input node exceeds by a first offset a voltage of the output current node;

wherein said control circuit comprises;

a first power supply node coupled to a first node of the startup current circuit;

a reference power supply node coupled to the output current node;

an input circuit having an input coupled to the disable input node, said input circuit configured to generate on an output node thereof a signal having different voltage and time characteristics relative to a signal coupled to its input node; and

a comparator circuit having a first input coupled to the input circuit output node, having a second input coupled to the output current node, and having an output coupled to an enable input for the startup current circuit, said comparator circuit configured to disable the startup current circuit when a voltage of the first input exceeds a voltage of the second input by a second offset.

29. The method as recited in claim 28 further comprising fabricating the startup circuit as a monolithic integrated circuit that is capable of operating with a voltage difference as high as 373 volts between the voltage input node and the output current node.

30. The method as recited in claim 29 further comprising encapsulating the monolithic integrated circuit using a low ionic content plastic compound to form a package that can tolerate steady-state power dissipation resulting from the startup current continuously flowing between the voltage input node and the output current node with a voltage difference as high as 373 volts between the voltage input node and the output current node.