Logical packet processing pipeline that retains state information to effectuate efficient processing of packets

• US 9,049,153 B2
• Filed: 08/26/2011
• Issued: 06/02/2015
• Est. Priority Date: 07/06/2010
• Status: Active Grant

• Current Assignee: Nicira Incorporated (Broadcom, Inc.)
• Original Assignee: Nicira Incorporated (Broadcom, Inc.)
• Inventors: Casado, Martin, Koponen, Teemu, Thakkar, Pankaj
• Primary Examiner(s): HSU, ALPUS
• Application Number:
  US13/218,464
• Publication Number:
  US 20130058342A1
• Time in Patent Office: 1,376 Days
• Field of Search: 370/235, 370/392, 370/397, 370/409, 370/428, 370/469, 709/201, 709/236, 709/238, 709/246, 712/28, 712/225
• US Class Current: 1/1
• CPC Class Codes: G06F 11/07 Responding to the occurrence of a fault, e.g. fault tolerance
• CPC Class Codes: G06F 15/17312 Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion routing on a LAN H04L45/00
• CPC Class Codes: H04L 12/4633 Interconnection of networks using encapsulation techniques, e.g. tunneling
• CPC Class Codes: H04L 2101/622 Layer-2 addresses, e.g. medium access control [MAC] addresses
• CPC Class Codes: H04L 41/0816 the condition being an adaptation, e.g. in response to network events
• CPC Class Codes: H04L 41/0853 by actively collecting configuration information or by backing up configuration information
• CPC Class Codes: H04L 41/0893 Assignment of logical groups to network elements
• CPC Class Codes: H04L 41/0894 Policy-based network configuration management
• CPC Class Codes: H04L 41/0895 Configuration of virtualised networks or elements, e.g. virtualised network function or OpenFlow elements
• CPC Class Codes: H04L 41/0896 Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities flow or congestion control using dynamic resource allocation, e.g. in-call renegotiation, H04L47/76
• CPC Class Codes: H04L 41/122 of virtualised topologies, e.g. software-defined networks [SDN] or network function virtualisation [NFV]
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/02 Topology update or discovery
• CPC Class Codes: H04L 45/036 Updating the topology between route computation elements, e.g. between OpenFlow controllers
• CPC Class Codes: H04L 45/586 of virtual routers
• CPC Class Codes: H04L 45/76 Routing in software-defined topologies, e.g. routing between virtual machines
• CPC Class Codes: H04L 47/783 Distributed allocation of resources, e.g. bandwidth brokers
• CPC Class Codes: H04L 49/00 Packet switching elements
• CPC Class Codes: H04L 49/1546 using pipelined operation
• CPC Class Codes: H04L 49/3063 Pipelined operation
• CPC Class Codes: H04L 49/70 : Virtual switches
• CPC Class Codes: H04L 61/5007 : Internet protocol [IP] addresses

Abstract

Some embodiments provide a method of processing a packet through a logical switching element implemented by several managed switching elements. The method receives a packet for processing through a processing pipeline of the logical switching element. The method processes the packet through the processing pipeline. The method stores state information in the packet for indicating that the packet has been processed through the processing pipeline in order to prevent other managed switching elements from processing the packet through the processing pipeline. The method forwards the processed packet to a managed switching element of the several managed switching elements.

Claims

1. A method of processing a packet at a first managed switching element that implements a logical switching element, along with a plurality of additional managed switching elements, the method comprising:

receiving, at an ingress port of the first managed switching element, a packet for processing through the logical switching element'"'"'s processing pipeline comprising a physical to logical mapping, logical processing, a logical to physical mapping, and physical processing;

processing the packet through a portion of the logical processing of the processing pipeline of the logical switching element at the first managed switching element, wherein the logical processing comprises processing the packet against a logical Layer 2 (L2) or Layer 3 (L3) forwarding table;

storing context information in the packet that indicates the portion of the processing pipeline through which the packet has been processed in order to prevent the additional managed switching elements from processing the packet through the same portion of the processing pipeline; and

forwarding the packet with the stored context information to a second managed switching element of the plurality of additional managed switching elements.

2. The method of claim 1, wherein processing the packet against the L2 forwarding table comprises performing a lookup on the logical L2 forwarding table based on information in a header of the packet.

3. The method of claim 1, wherein processing the packet against the L3 forwarding table comprises performing a lookup on the L3 layer forwarding table based on information in a header of the packet.

4. The method of claim 1, wherein the logical processing comprises performing a lookup on the logical L2 or L3 forwarding table to identify a logical outport of the logical switching element for the packet based on address information stored in a header of the packet.

5. The method of claim 4, wherein the logical to physical mapping comprises identifying a physical output port that corresponds to the identified logical outport of the logical switching element in order to forward the packet to the second managed switching element.

6. The method of claim 1, wherein the physical to logical mapping comprises identifying that the packet belongs to the logical switching element.

7. The method of claim 6, wherein identifying that the packet belongs to the logical switching element comprises using the ingress port of the first managed switching element at which the packet is received.

8. The method of claim 1, wherein the context information is stored in a set of fields in a header of the packet.

9. The method of claim 8, wherein the set of fields comprises a logical inport field for indicating a port of the logical switching element at which the packet originated.

10. The method of claim 8, wherein the set of fields comprises a logical outport field for indicating a port of the logical switching element to which to send the packet.

11. The method of claim 8, wherein the set of fields comprises a virtual routing and forwarding field for indicating a logical forwarding table with which to process the packet.

12. The method of claim 1, wherein processing the packet through the portion of the logical processing of the processing pipeline comprises generating the context information for storing in the packet.

13. The method of claim 1, wherein the logical processing of the processing pipeline further comprises processing the packet against a logical ingress or egress access control list (ACL).

14. The method of claim 1, wherein the portion of the logical processing of the processing pipeline is a first portion, wherein the second managed switching element is for processing the packet through a second portion based on the stored context information in the packet.

15. The method of claim 14, wherein the logical processing of the processing pipeline further comprises a logical ingress access control list (ACL) decision and a logical egress ACL decision, wherein the logical processing comprises a logical forwarding decision based on the L2 or L3 forwarding table, wherein the first portion comprises the logical ingress ACL decision and the logical forwarding decision, and the second portion comprises the logical egress ACL decision.

16. A non-transitory machine readable medium storing a program which when executed by at least one processing unit processes a packet at a first managed switching element that implements a logical switching element, along with a plurality of additional managed switching elements, the program comprising sets of instructions for:

receiving, at an ingress port of the first managed switching element, a packet for processing through the logical switching element'"'"'s processing pipeline comprising a physical to logical mapping, logical processing, a logical to physical mapping, and physical processing;

processing the packet through a portion of the logical processing of the processing pipeline of the logical switching element at the first managed switching element, wherein the logical processing comprises processing the packet against a logical Layer 2 (L2) or Layer 3 (L3) forwarding table;

storing context information in the packet that indicates the portion of the processing pipeline through which the packet has been processed in order to prevent the additional managed switching elements from processing the packet through the same portion of the processing pipeline; and

forwarding the packet with the stored context information to a second managed switching element of the plurality of additional managed switching elements.

17. The non-transitory machine readable medium of claim 16, wherein the set of instructions for processing the packet through the portion of the logical processing of the processing pipeline comprises a set of instructions for performing the logical processing by performing a lookup on the logical L2 forwarding table based on a media access control (MAC) address in a header of the packet in order to identify a logical outport on the logical switching element.

18. The non-transitory machine readable medium of claim 17, wherein the set of instructions for processing the packet comprises a set of instructions for performing the logical to physical mapping by identifying a physical output port that corresponds to the identified logical outport of the logical switching element in order to forward the packet to the second managed switching element.

19. The non-transitory machine readable medium of claim 16, wherein the set of instructions for processing the packet through the portion of the logical processing of the processing pipeline comprises a set of instructions for performing the physical to logical mapping by identifying an inport of the logical switching element based on the ingress port of the first managed switching element at which the packet was received.

20. The non-transitory machine readable medium of claim 16, wherein the context information is stored in a header of the packet.

21. The non-transitory machine readable medium of claim 20, wherein the context information stored in the header of the packet comprises at least a logical outport of the logical switching element determined by the processing pipeline.

22. The non-transitory machine readable medium of claim 16, wherein the set of instructions for processing the packet through the portion of the logical processing of the processing pipeline comprises a set of instructions for performing the logical processing by generating the context information to store in the packet.

23. The non-transitory machine readable medium of claim 16, wherein the logical processing of the processing pipeline further comprises processing the packet against a ingress or egress logical access control list (ACL).

24. The non-transitory machine readable medium of claim 16, wherein the program executes on a host device to implement the first managed switching element.