Patch field documentation and revision systems

• US 9,049,499 B2
• Filed: 07/17/2009
• Issued: 06/02/2015
• Est. Priority Date: 08/26/2005
• Status: Active Grant

• Current Assignee: Panduit Corporation
• Original Assignee: Panduit Corporation
• Inventors: Nordin, Ronald A., Caveney, Jack E.
• Primary Examiner(s): Riyami, Abdullah
• Assistant Examiner(s): Imas, Vladimir
• Application Number:
  US12/505,280
• Publication Number:
  US 20090275216A1
• Time in Patent Office: 2,146 Days
• Field of Search: 439/49, 439/955, 439/488, 439/490
• US Class Current: 1/1
• CPC Class Codes: H04Q 1/136 having patch field management or physical layer management arrangements
• CPC Class Codes: Y10S 439/955 including electronic identifier or coding means

Abstract

A communication network device and corresponding patch field system are disclosed. The device includes a port module, ports, and an appliqué attached to a face of the port module. The appliqué includes a printed circuit board (PCB) with conductive pads. A patch cord connects the device with an intelligent patch panel. The patch cord contains at least one system wire. The patch panel is adapted to measure a resistance associated with each port via the system wire. An open circuit indicates that no patch cord is attached to the port, a resistance within a first range indicates that the patch cord is attached only to the port of the intelligent patch panel, and a resistance within a second range less than the first range indicates that the patch cord connects the intelligent patch panel and the device.

Claims

1. An appliqué

for use with a patch panel in a mapping system comprising;

first and second conductive pads, the first and second conductive pads associated with a first port of the patch panel;

a first signature resistance in series with a first diode, the orientation of the first diode requiring the first signature resistance to be measured between the first and second conductive pads with a forward bias or polarity; and

a second signature resistance in series with a second diode, the orientation of the second diode requiring the second signature resistance to be measured between the first and second conductive pads with a reverse bias or polarity, the first signature resistance being different than the second signature resistance.

2. The appliqué

of claim 1 further comprising;

third and fourth conductive pads, the third and fourth conductive pads associated with a second port of the patch panel;

a third signature resistance in series with a third diode, the orientation of the third diode requiring the third signature resistance to be measured between the third and fourth conductive pads with a forward bias or polarity;

a fourth signature resistance in series with a fourth diode, the orientation of the fourth diode requiring the fourth signature resistance to be measured between the third and fourth conductive pads with a reverse bias or polarity, the third signature resistance being different from the first, second, and fourth signature resistances, the fourth signature resistance being equal to the second signature resistance.

3. The appliqué

of claim 2 further comprising a frame, a printed circuit board, and a cover.

4. The appliqué

of claim 3 wherein the frame is made of a clear material.

5. The appliqué

of claim 4 further comprising light emitting diodes.

6. The appliqué

of claim 5 wherein the frame comprises reflectors formed therein to optically isolate the light emitting diodes from each other.