Packet switch based logic replication

• US 9,052,357 B2
• Filed: 01/24/2014
• Issued: 06/09/2015
• Est. Priority Date: 01/22/2010
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Erickson, Robert
• Primary Examiner(s): Sheikh, Ayaz
• Assistant Examiner(s): HAMPTON, TARELL A
• Application Number:
  US14/162,757
• Publication Number:
  US 20140137056A1
• Time in Patent Office: 501 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31726 Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals
• CPC Class Codes: G06F 11/36 Preventing errors by testing or debugging software
• CPC Class Codes: G06F 11/362 Software debugging
• CPC Class Codes: G06F 11/3632 of specific synchronisation aspects
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/35 Delay-insensitive circuit design, e.g. asynchronous or self-timed
• CPC Class Codes: G06F 30/396 Clock trees

Abstract

A method for debugging comprising configuring a switching logic mapping source subchannels to destination subchannels, as virtual channels to forward the packets from the source subchannels to the destination subchannels. The method further comprising configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronously with the plurality of clock domains with the delay period.

Claims

1. A method for debugging a source circuit, the method comprising upon receiving information regarding the source circuit:

compiling representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains, each source subchannel to generate packets carrying signal data from one of the portions of the source logic;

compiling representation of a destination circuit including one or more destination subchannels associated with portions of destination logic replicating the source logic, each destination subchannel to forward the signal data via the packets to one of the portions of the destination logic;

configuring a switching logic mapping the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels, the packets based on a packet format including a header field and a payload field, the header field to carry channel identifiers identifying the virtual channels and the payload field to carry the signal data; and

configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronous with the plurality of clock domains with the delay period.

2. The method of claim 1, wherein the switch logic is based on one or more programmable logic devices loaded with binary code representing the switch logic, the method further comprising:

compiling a source code representing the switch logic to generate the binary code.

3. The method of claim 2, wherein the programmable logic device is a FPGA (Field Programmable Logic Array) device.

4. The method of claim 1, wherein each packet includes one of the channel identifiers identifying one of the virtual channels mapping the source subchannel to one of the destination subchannels.

5. The method of claim 4, wherein the source subchannel includes packing logic to pack the one of the channel identifiers into the packets with the signal data.

6. The method of claim 4, wherein the one of the destination subchannels includes unpacking logic to extract the signal data from the packets.

7. The method of claim 1, wherein the packets from the source subchannels are popped out from and pushed into the single queue at a substantially equal rate.

8. The method of claim 1, wherein the switching logic includes a read only storage storing definitions for the virtual channels.

9. A method for logic emulation, the method comprising upon initializing a logic emulation system:

in response to receiving packets from source logic in series via an interface, decoding an identifier from each packet to identify one of a plurality of portions of destination logic cloning the source logic, the packets being formatted according to a packet format including a header field and a payload field, the header field for carrying the identifier, the payload field for carrying signal data for the identified portion of the destination logic;

storing the packet to one of a plurality of queues associated with the identified portion of the destination logic;

unpacking the signal data from the packet from the one of the plurality of queues according to the packet format; and

providing the signal data to the identified portion of the destination logic synchronized with the source logic.

10. The method of claim 9, wherein the destination logic and the source logic are driven by a plurality of clock domains, and wherein each portion of the destination logic belongs to one of the clock domains.

11. A method for logic emulation, the method comprising upon initializing a logic emulation system:

in response to receiving packets from source logic, storing the packets in a plurality of receiver queues, the packets carrying signal data from a plurality of portions of the source logic for replication in a plurality of portions of destination logic cloning the source logic, the packets identifying virtual channels mapping the plurality of portions of the source logic to the plurality of portions of the destination logic;

arbitrating the packets from the receiver queues to a buffer queue as a trace of the signal data of the source logic for a period;

updating the packets retrieved from the buffer queue with destination identifiers identifying the plurality of portions of the destination logic according to the virtual channels; and

distributing the packets updated for the plurality of portions of the destination logic identified to forward the signal data to the destination logic synchronized with the source logic.

12. The method of claim 11, wherein the distribution is based on a plurality of interfaces to the destination logic, the plurality of interfaces being associated with interface queues, the distribution comprises:

storing the packets to the interface queues according to the destination identifiers.

13. The method of claim 12, wherein the destination logic includes a plurality of chips, each interface to couple with one of the chips.

14. The method of claim 12, further comprising:

synchronizing the interfaces for receiving the packets when the buffer is substantially full.

15. The method of claim 14, wherein the synchronization comprises:

counting a counter, wherein the distribution is subsequent to completion of the counting.

16. The method of claim 11, wherein the source logic is driven by a plurality of clock domains, and wherein each of the plurality of portions of the source logic belongs to one of the clock domains.

17. The method of claim 16, wherein the destination logic is driven by the plurality of clock domains.

18. The method of claim 11, wherein the packets arrive in a temporal order and wherein the arbitration maintains an order for the packets in the buffer substantially following the temporal order within a known margin.

19. The method of claim 11, wherein the packets are formatted with a header field, the update of the packets comprises:

decoding identifiers from the header field of the packets, the identifiers identifying the virtual channels formatted with a packet type field, wherein the packets are distributed to the destination logic according to a type indication of the packet type field.

20. The method of claim 19, wherein the virtual channels are formatted with a memory space field for memory space identifiers, wherein the type indication for one of the packets indicates a memory write operation, the method further comprising:

decoding a memory address and data from the one packet; and

writing the data to the memory address in a memory space identified by one of the memory space identifier.

21. An article of manufacture comprising:

a non-transitory machine accessible medium including content that when accessed by a machine causes the machine to perform operations including;

selecting a plurality of portions of source logic for replication;

inserting packing logic to the source logic, the packing logic generating packets representing signal data of the selected portions, each packet including a source identifier identifying one of the selected portion;

replicating the selected portions of the source logic in destination logic;

inserting unpacking logic to the destination logic, the unpacking logic configuring logic to extract the signal data from received packets for the replicated portions, each received packet including a destination identifier identifying one of the replicated portions; and

configuring a switching logic mapping the destination identifiers to the source identifiers as virtual channels to forward the signal data from the selected portions to the replicated portions via delay logic recording a trace of the signal data over a delay period.

22. The article of manufacture of claim 21, wherein the packets are based on a packet format including a header field and a payload field, the header field to carry channel identifiers identifying the virtual channels and the payload field to carry the signal data.