Packet switch based logic replication
First Claim
Patent Images
1. A method for debugging a source circuit, the method comprising upon receiving information regarding the source circuit:
- compiling representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains, each source subchannel to generate packets carrying signal data from one of the portions of the source logic;
compiling representation of a destination circuit including one or more destination subchannels associated with portions of destination logic replicating the source logic, each destination subchannel to forward the signal data via the packets to one of the portions of the destination logic;
configuring a switching logic mapping the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels, the packets based on a packet format including a header field and a payload field, the header field to carry channel identifiers identifying the virtual channels and the payload field to carry the signal data; and
configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronous with the plurality of clock domains with the delay period.
0 Assignments
0 Petitions
Accused Products
Abstract
A method for debugging comprising configuring a switching logic mapping source subchannels to destination subchannels, as virtual channels to forward the packets from the source subchannels to the destination subchannels. The method further comprising configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronously with the plurality of clock domains with the delay period.
-
Citations
22 Claims
-
1. A method for debugging a source circuit, the method comprising upon receiving information regarding the source circuit:
-
compiling representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains, each source subchannel to generate packets carrying signal data from one of the portions of the source logic; compiling representation of a destination circuit including one or more destination subchannels associated with portions of destination logic replicating the source logic, each destination subchannel to forward the signal data via the packets to one of the portions of the destination logic; configuring a switching logic mapping the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels, the packets based on a packet format including a header field and a payload field, the header field to carry channel identifiers identifying the virtual channels and the payload field to carry the signal data; and configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronous with the plurality of clock domains with the delay period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A method for logic emulation, the method comprising upon initializing a logic emulation system:
-
in response to receiving packets from source logic in series via an interface, decoding an identifier from each packet to identify one of a plurality of portions of destination logic cloning the source logic, the packets being formatted according to a packet format including a header field and a payload field, the header field for carrying the identifier, the payload field for carrying signal data for the identified portion of the destination logic; storing the packet to one of a plurality of queues associated with the identified portion of the destination logic; unpacking the signal data from the packet from the one of the plurality of queues according to the packet format; and providing the signal data to the identified portion of the destination logic synchronized with the source logic. - View Dependent Claims (10)
-
-
11. A method for logic emulation, the method comprising upon initializing a logic emulation system:
-
in response to receiving packets from source logic, storing the packets in a plurality of receiver queues, the packets carrying signal data from a plurality of portions of the source logic for replication in a plurality of portions of destination logic cloning the source logic, the packets identifying virtual channels mapping the plurality of portions of the source logic to the plurality of portions of the destination logic; arbitrating the packets from the receiver queues to a buffer queue as a trace of the signal data of the source logic for a period; updating the packets retrieved from the buffer queue with destination identifiers identifying the plurality of portions of the destination logic according to the virtual channels; and distributing the packets updated for the plurality of portions of the destination logic identified to forward the signal data to the destination logic synchronized with the source logic. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
-
21. An article of manufacture comprising:
a non-transitory machine accessible medium including content that when accessed by a machine causes the machine to perform operations including; selecting a plurality of portions of source logic for replication; inserting packing logic to the source logic, the packing logic generating packets representing signal data of the selected portions, each packet including a source identifier identifying one of the selected portion; replicating the selected portions of the source logic in destination logic; inserting unpacking logic to the destination logic, the unpacking logic configuring logic to extract the signal data from received packets for the replicated portions, each received packet including a destination identifier identifying one of the replicated portions; and configuring a switching logic mapping the destination identifiers to the source identifiers as virtual channels to forward the signal data from the selected portions to the replicated portions via delay logic recording a trace of the signal data over a delay period. - View Dependent Claims (22)
Specification