Semiconductor structure and method of generating masks for making integrated circuit
First Claim
1. A method of generating masks for making an integrated circuit, the masks comprising layout patterns corresponding to first and second groups of conductive paths of the integrated circuit, and the method comprising:
- determining, by a hardware processor, if a coupling capacitance value of a conductive path of the first and second groups of conductive paths is greater than a predetermined threshold value, the determination being performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined level of mask misalignment; and
modifying the layout patterns to increase an overall vertical distance between the first group of conductive paths and the second group of conductive paths if the coupling capacitance value is greater than the predetermined threshold value.
1 Assignment
0 Petitions
Accused Products
Abstract
A method of generating masks for making an integrated circuit includes determining if a coupling capacitance value of a conductive path of a first and second groups of conductive paths of the integrated circuit is greater than a predetermined threshold value. The determination is performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined level of mask misalignment. The layout patterns are modified to increase an overall vertical distance between the first group of conductive paths and the second group of conductive paths if the coupling capacitance value is greater than the predetermined threshold value.
-
Citations
29 Claims
-
1. A method of generating masks for making an integrated circuit, the masks comprising layout patterns corresponding to first and second groups of conductive paths of the integrated circuit, and the method comprising:
-
determining, by a hardware processor, if a coupling capacitance value of a conductive path of the first and second groups of conductive paths is greater than a predetermined threshold value, the determination being performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined level of mask misalignment; and modifying the layout patterns to increase an overall vertical distance between the first group of conductive paths and the second group of conductive paths if the coupling capacitance value is greater than the predetermined threshold value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. A method of simulating coupling capacitance variation of a plurality of conductive paths of the integrated circuit caused by misalignment of masks for making the plurality of conductive paths, the plurality of conductive paths is arranged in parallel, and the method comprising:
-
generating a table listing combinations of one or more predetermined conductive paths of the plurality of conductive paths and types of misalignment between a corresponding one of the masks against the remaining of the masks; identifying a subset of combinations that do not correspond to shifting a corresponding conductive path of the plurality of conductive paths between two adjacent conductive paths of the plurality of conductive paths; and calculating, by a hardware processor, a coupling capacitance value based on one combination of the subset of combinations. - View Dependent Claims (17, 18, 19)
-
-
20. A method of generating layout patterns for making first and second conductive paths of an integrated circuit, the first and second conductive paths being in parallel along a predetermined direction, the method comprising:
-
dividing a first line pattern representative of the first conductive path into a first set of segments; dividing a second line pattern representative of the second conductive path into a second set of segments; grouping the first set of segments and the second set of segments into; a first group of segments containing odd-ordered segments of the first set of segments and even-ordered segments of the second set of segments; and a second group of segments containing even-ordered segments of the first set of segments and odd-ordered segments of the second set of segments; assigning layout patterns of the odd-ordered segments in the first group of segments to a first mask; assigning layout patterns of the even-ordered segments in the first group of segments to a second mask; assigning layout patterns of odd-ordered segments in the second group of segments to a third mask; and assigning layout patterns of even-ordered segments in the first group of segments to a fourth mask. - View Dependent Claims (21)
-
-
22. A method of generating layout patterns corresponding to a first conductive layer and a second conductive layer of an integrated circuit, the method comprising:
-
dividing a first line pattern representative of a first conductive path into a first set of segments; dividing a second line pattern representative of a second conductive path into a second set of segments, wherein the first and the second conductive paths are parallel along a predetermined direction; assigning layout patterns corresponding to a first portion of the first set of segments to a first mask, the first mask corresponding to the first conductive layer; assigning layout patterns corresponding to a second portion of the first set of segments to a second mask, the second mask corresponding to the second conductive layer; assigning layout patterns corresponding to a first portion of the second set of segments to a third mask, the third mask corresponding to the first conductive layer; and assigning layout patterns corresponding to a second portion of the second set of segments to a fourth mask, the fourth mask corresponding to the second conductive layer. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
-
Specification