Signal line driver circuit and liquid crystal display device
First Claim
Patent Images
1. A driver circuit comprising:
- a shift register;
a selection circuit having a function of determining that a pulse signal input from the shift register is output as a first pulse signal or a second pulse signal, in accordance with a first clock signal and a second clock signal; and
a driving signal output circuit having functions of generating and outputting a driving signal for controlling a potential of a signal line in accordance with the first and second pulse signals input from the selection circuit and a first control signal and a second control signal,wherein the driving signal output circuit comprises;
a latch unit configured to write and store first data and second data in accordance with the first and second pulse signals;
a buffer unit configured to set a potential of the driving signal in accordance with the first data and the second data and output the driving signal; and
a switch unit configured to control pull-up of the latch unit output of only the first data by being turned on or off in accordance with the first control signal and the second control signal so as to suppress a change in a potential of the first data.
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Abstract
To prevent malfunctions from occurring. A shift register, a selection circuit having a function of determining which a first pulse signal or a second pulse signal is output at the same potential level as a pulse signal input from the shift register, and a plurality of driving signal output circuits each having functions of generating and outputting a driving signal are provided. Each of the plurality of driving signal output circuits includes a latch unit, a buffer unit, and a switch unit for controlling rewriting of data stored in the latch unit.
108 Citations
14 Claims
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1. A driver circuit comprising:
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a shift register; a selection circuit having a function of determining that a pulse signal input from the shift register is output as a first pulse signal or a second pulse signal, in accordance with a first clock signal and a second clock signal; and a driving signal output circuit having functions of generating and outputting a driving signal for controlling a potential of a signal line in accordance with the first and second pulse signals input from the selection circuit and a first control signal and a second control signal, wherein the driving signal output circuit comprises; a latch unit configured to write and store first data and second data in accordance with the first and second pulse signals; a buffer unit configured to set a potential of the driving signal in accordance with the first data and the second data and output the driving signal; and a switch unit configured to control pull-up of the latch unit output of only the first data by being turned on or off in accordance with the first control signal and the second control signal so as to suppress a change in a potential of the first data. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A driver circuit comprising:
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a shift register; a selection circuit having a function of determining that a pulse signal input from the shift register is output as a first pulse signal or a second pulse signal, in accordance with a first clock signal and a second clock signal; and a driving signal output circuit having functions of generating and outputting a driving signal for controlling a potential of a signal line in accordance with the first and second pulse signals input from the selection circuit and a first control signal, a second control signal, a third control signal, a fourth control signal, and a fifth control signal, wherein the driving signal output circuit comprises; a first latch unit configured to write and store first data and second data in accordance with the first and second pulse signals; a second latch unit configured to write and store third data and fourth data in accordance with the first and second pulse signals; a first buffer unit configured to set a potential of the first signal in accordance with the first data and the second data and output the first signal; a second buffer unit configured to set a potential of the second signal in accordance with the third data and the fourth data and output the second signal; a first switch unit configured to control pull-up of the first latch unit output of only the first data by being turned on or off in accordance with the first control signal and the second control signal so as to suppress a change in a potential of the first data; a second switch unit configured to control pull-up of the second latch unit output of the third data by being turned on or off in accordance with the first control signal and the third control signal so as to suppress a change in a potential of the third data; a third switch unit to which the second signal is input as the fourth control signal and that is configured to control pull-up of the first latch unit output of the second data by being turned on or off in accordance with the fourth control signal so as to suppress a change in a potential of the second data; a fourth switch unit to which the first signal is input as the fifth control signal and that is configured to control pull-up of the second latch unit output of the fourth data by being turned on or off in accordance with the fifth control signal so as to suppress a change in a potential of the fourth data; and a third buffer unit configured to set a potential of the driving signal in accordance with the first signal and the second signal and output the driving signal. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification