Memory controller that enforces strobe-to-strobe timing offset

• US 9,053,778 B2
• Filed: 12/12/2013
• Issued: 06/09/2015
• Est. Priority Date: 04/24/2001
• Status: Expired due to Fees

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US14/104,188
• Publication Number:
  US 20140098622A1
• Time in Patent Office: 544 Days
• Field of Search: 365/154, 365/191, 365/193, 365/233.1, 365/221
• US Class Current: 1/1
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory controller outputs a clock signal to first and second DRAMs disposed on a memory module, the clock signal requiring respective first and second time intervals to propagate to the first and second DRAMs. The memory controller outputs a write command to be sampled by the first and second DRAMs at times indicated by the first clock signal and outputs, in association with the write command, first and second write data to the first and second DRAMs, respectively. The memory controller further outputs first and second strobe signals respectively to the first and second DRAMs, the first strobe signal to time reception of the first and second write data therein. The memory controller adjusts respective transmission times of the first and second strobe signals to be offset from one another by a time interval that corresponds to a difference between the first and second time intervals.

Claims

1. A method of operation within a memory controller component, the method comprising:

transmitting a clock signal to first and second dynamic random access memory (DRAM) components disposed on a memory module via a clock signal line, the clock signal line being coupled to the first and second DRAM components at different points along its length such that the clock signal propagates past the first DRAM component to the second DRAM component, the clock signal having a first arrival time at the first DRAM and a second arrival time at the second DRAM, the first arrival time preceding the second arrival time;

transmitting a write command to the first and second DRAM components via a set of signal lines, the write command to be sampled by the first and second DRAM components at respective times corresponding to one or more transitions of the clock signal, the set of signal lines being coupled to the first and second DRAM components at different points along its length such that the write command propagates past the first DRAM component to the second DRAM component and arrives at the first DRAM component before arriving at the second DRAM component;

transmitting, in association with the write command, first write data to the first DRAM component and second write data to the second DRAM component;

generating a first strobe signal to time reception of the first write data within the first DRAM component, wherein a phase of the first strobe signal is adjusted to compensate for skew between an arrival time, at the first DRAM component, of the first strobe signal and the first arrival time of the clock signal; and

generating a second strobe signal to time reception of the second write data within the second DRAM component, wherein a phase of the second strobe signal is adjusted to compensate for skew between an arrival time, at the second DRAM component, of the second strobe signal and the second arrival time of the clock signal.

2. The method of claim 1 further comprising transmitting a write address to be sampled by the first and second DRAM components at respective times corresponding to the one or more transitions of the clock signal, wherein the write command instructs the first and second DRAM components to store the first write data and second write data at respective storage locations within the first and second DRAM components indicated by the write address.

3. The method of claim 1 wherein the clock signal requires a first time interval to propagate from the memory controller component to the first DRAM component, and a second time interval to propagate from the memory controller component to the second DRAM component, and wherein the first and second strobe signals are adjusted to have respective transmission times offset from one another by a time interval that corresponds, at least in part, to a difference between the first and second time intervals.

4. The method of claim 1 further comprising generating a plurality of incrementally delayed signals, and wherein transmitting the first and second write data to the first and second DRAM components comprises transmitting the first and second write data respectively to the first and second DRAM components in response to respective first and second ones of the incrementally delayed signals.

5. The method of claim 4 wherein generating the plurality of incrementally delayed signals comprises generating the plurality of incrementally delayed signals in a plurality of delay elements coupled in series, each of the delay elements generating a respective one of the incrementally delayed signals.

6. The method of claim 5 wherein the plurality of delay elements comprises part of a delay locked loop.

7. The method of claim 6 wherein the delay locked loop adjusts respective delays of the delay elements to control a total delay of the delay locked loop.

8. The method of claim 4 wherein transmitting the first write data to the first DRAM component comprises storing the first write data in a shift register and shifting the first write data out of the shift register in response to transitions of the first one of the incrementally delayed signals.

9. A memory controller component comprising:

clock transmit circuitry to transmit a clock signal to first and second dynamic random access memory (DRAM) components disposed on a memory module via a clock line, the clock line being coupled to the first and second DRAM components at different points along its length such that the clock signal propagates past the first DRAM component to the second DRAM component, the clock signal having a first arrival time at the first DRAM and a second arrival time at the second DRAM, the first arrival time preceding the second arrival time;

command transmit circuitry to transmit a write command to the first and second DRAM components via a set of signal lines, the write command to be sampled by the first and second DRAM components at respective times corresponding to one or more transitions of the clock signal, the set of signal lines being coupled to the first and second DRAM components at different points along its length such that the write command propagates past the first DRAM component to the second DRAM component and arrives at the first DRAM component before arriving at the second DRAM component; and

data transmit circuitry to transmit, in association with the write command, first write data to the first DRAM component and second write data to the second DRAM component,

wherein the first write data is transmitted along with a first strobe signal to time reception of the first write data within the first DRAM component, wherein a phase of the first strobe signal is adjusted to compensate for skew between an arrival time, at the first DRAM component, of the first strobe signal and the first arrival time of the clock signal, and

wherein the second write data is transmitted along with a second strobe signal to time reception of the second write data within the second DRAM component, wherein a phase of the second strobe signal is adjusted to compensate for skew between an arrival time, at the second DRAM component, of the second strobe signal and the second arrival time of the clock signal.

10. The memory controller component of claim 9 further comprising address transmit circuitry to transmit a write address to be sampled by the first and second DRAM components at respective times corresponding to the one or more transitions of the clock signal, wherein the write command instructs the first and second DRAM components to store the first write data and second write data at respective storage locations within the first and second DRAM components indicated by the write address.

11. The memory controller component of claim 9 wherein the clock signal requires a first time interval to propagate from the memory controller component to the first DRAM component, and a second time interval to propagate from the memory controller component to the second DRAM component, and wherein the first and second strobe signals are adjusted to have respective transmission times offset from one another by a time interval that corresponds, at least in part, to a difference between the first and second time intervals.

12. The memory controller component of claim 9 further comprising timing circuitry to generate a plurality of incrementally delayed signals, and wherein the data transmit circuitry to transmit the first and second write data to the first and second DRAM components comprises circuitry to transmit the first and second write data respectively to the first and second DRAM components in response to respective first and second ones of the incrementally delayed signals.

13. The memory controller component of claim 12 wherein the circuitry to generate the plurality of incrementally delayed signals comprises a plurality of delay elements coupled in series, each of the delay elements generating a respective one of the incrementally delayed signals.

14. The memory controller component of claim 13 wherein the plurality of delay elements comprises part of a delay locked loop.

15. The memory controller component of claim 14 wherein the delay locked loop comprises circuitry to adjust respective delays of the delay elements to control a total delay of the delay locked loop.

16. The memory controller component of claim 12 wherein the data transmit circuitry to transmit the first write data to the first DRAM component comprise a shift register to store the first write data and circuitry to shift the first write data out of the shift register in response to transitions of the first one of the incrementally delayed signals.

17. The memory controller component of claim 9 further comprising a delay locked loop to generate a plurality of incrementally delayed signals, and wherein the circuitry to transmit the first and second write data to the first and second DRAM components comprises circuitry to transmit the first and second write data respectively to the first and second DRAM components in response to respective first and second ones of the incrementally delayed signals.

18. The memory controller component of claim 17 wherein the circuitry to transmit the first write data to the first DRAM component comprises a shift register to store the first write data and circuitry to shift the first write data out of the shift register in response to transitions of the first one of the incrementally delayed signals.

19. A memory controller component comprising:

circuitry to transmit a clock signal and a write command to first and second dynamic random access memory (DRAM) components disposed on a memory module via control signal lines, the control signal lines being coupled to the first and second DRAM components at different points along their lengths such that the clock signal and write command propagate past the first DRAM component to the second DRAM component, arriving at the first DRAM at a first arrival time and arriving at the second DRAM at a later, second arrival time; and

circuitry to transmit, in association with the write command, first write data to the first DRAM component and second write data to the second DRAM component,

wherein the first write data is transmitted along with a first strobe signal to time reception of the first write data within the first DRAM component, wherein a phase of the first strobe signal is adjusted to compensate for skew between an arrival time, at the first DRAM component, of the first strobe signal and the first arrival time of the clock signal, and

wherein the second write data is transmitted along with a second strobe signal to time reception of the second write data within the second DRAM component, wherein a phase of the second strobe signal is adjusted to compensate for skew between an arrival time, at the second DRAM component, of the second strobe signal and the second arrival time of the clock signal.

20. The memory controller component of claim 19 wherein the clock signal requires a first time interval to propagate from the memory controller component to the first DRAM component, and a second time interval to propagate from the memory controller component to the second DRAM component, and wherein the first and second strobe signals are adjusted to have respective transmission times offset from one another by a time interval that corresponds, at least in part, to a difference between the first and second time intervals.