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Memory controller that enforces strobe-to-strobe timing offset

  • US 9,053,778 B2
  • Filed: 12/12/2013
  • Issued: 06/09/2015
  • Est. Priority Date: 04/24/2001
  • Status: Expired due to Fees
First Claim
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1. A method of operation within a memory controller component, the method comprising:

  • transmitting a clock signal to first and second dynamic random access memory (DRAM) components disposed on a memory module via a clock signal line, the clock signal line being coupled to the first and second DRAM components at different points along its length such that the clock signal propagates past the first DRAM component to the second DRAM component, the clock signal having a first arrival time at the first DRAM and a second arrival time at the second DRAM, the first arrival time preceding the second arrival time;

    transmitting a write command to the first and second DRAM components via a set of signal lines, the write command to be sampled by the first and second DRAM components at respective times corresponding to one or more transitions of the clock signal, the set of signal lines being coupled to the first and second DRAM components at different points along its length such that the write command propagates past the first DRAM component to the second DRAM component and arrives at the first DRAM component before arriving at the second DRAM component;

    transmitting, in association with the write command, first write data to the first DRAM component and second write data to the second DRAM component;

    generating a first strobe signal to time reception of the first write data within the first DRAM component, wherein a phase of the first strobe signal is adjusted to compensate for skew between an arrival time, at the first DRAM component, of the first strobe signal and the first arrival time of the clock signal; and

    generating a second strobe signal to time reception of the second write data within the second DRAM component, wherein a phase of the second strobe signal is adjusted to compensate for skew between an arrival time, at the second DRAM component, of the second strobe signal and the second arrival time of the clock signal.

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