Internal data load for non-volatile storage

• US 9,053,820 B2
• Filed: 08/11/2014
• Issued: 06/09/2015
• Est. Priority Date: 03/05/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Chen, Wenzhou, Lee, Dana, Zhou, Zhenming, Liang, Guirong
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US14/456,984
• Publication Number:
  US 20140347925A1
• Time in Patent Office: 302 Days
• Field of Search: 365/185.2, 365/185.18, 365/185.03, 365/185.23, 365/185.17, 365/185.21
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Abstract

Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.

Claims

1. A method of operating non-volatile storage, comprising:

starting to program a first upper page into a first group of non-volatile storage elements associated with a first word line, the first group of non-volatile storage elements are to be programmed to a plurality of data states;

pausing programming of the first upper page when programming of a first data state of the plurality of data states is complete;

reading a lower page of data from a second group of non-volatile storage elements associated with a second word line while programming of the first upper page is paused, the second word line is adjacent to the first word line;

storing the lower page of data in a set of latches;

completing the programming of the first upper page into the first group non-volatile storage elements after storing the lower page; and

programming a second upper page of data into the second group non-volatile storage elements based on the lower page of data stored in the set of latches, the programming of the second upper page occurs after completing the programming of the first upper page into the first group of non-volatile storage elements.

2. The method of claim 1, wherein the lower page of data is a first lower page of data, the programming a second upper page of data into the second group of non-volatile storage elements based on the first lower page stored in the set of latches comprises:

preserving the first lower page of data in the set of latches while programming a second lower page of data in a third word line that is adjacent to the second word line; and

programming the second upper page of data into the second group non-volatile storage elements based on the preserved first lower page of data.

3. The method of claim 1, wherein programming the second upper page of data into the second group non-volatile storage elements based on the lower page stored in the set of latches comprises:

re-programming the lower page into the second group of non-volatile storage elements based on the data stored in the set of latches.

4. The method of claim 3, wherein the re-programming the lower page into the second group of non-volatile storage elements comprises:

using a higher verify level compared to a verify level used when the lower page was previously programmed into the second group of non-volatile storage elements.

5. The method of claim 3, further comprising:

reading, into the set of latches, the lower page data that was re-programmed into the second group of non-volatile storage elements; and

using the lower page data that was read into the set of latches after the re-programming when programming the second upper page of data into the second group non-volatile storage elements.

6. The method of claim 1, wherein the plurality of data states include an erase state and three programmed states, the first data state is a lowest of the programmed states.

7. The method of claim 1, wherein each non-volatile storage element of the first group of non-volatile storage elements is part of one of a plurality of NAND strings, each non-volatile storage element of the second group of non-volatile storage elements is part of one of the plurality of NAND strings.

8. The method of claim 1, wherein the first group of non-volatile storage elements and the second group of non-volatile storage elements are included within in a three-dimensional memory array.

9. A non-volatile storage device, comprising:

a plurality of non-volatile storage elements;

a set of latches associated with the plurality of non-volatile storage elements;

a plurality of word lines associated with the plurality non-volatile storage elements, the word lines include a target word line, a first neighbor word line on one side of the target word line and a second neighbor word line on the other side of the target word line; and

one or more managing circuits in communication with the plurality non-volatile storage elements, the set of latches, and the plurality of word lines, the one or more managing circuits start to program a first upper page into a first group of the plurality of non-volatile storage elements associated with the first neighbor word line, the first group of non-volatile storage elements are to be programmed to a plurality of data states, the one or more managing circuits determine when programming of a first data state of the plurality of data states is complete, the one or more managing circuits pause programming of the first upper page into the first group of non-volatile storage elements in response to the first data state programming being complete, the one or more managing circuits read a lower page of data from a second group of the plurality of non-volatile storage elements associated with the target word line while the programming is paused, the one or more managing circuits store the lower page of data in the set of latches, the one or more managing circuits complete the programming of the first upper page into the first group non-volatile storage elements after storing the lower page of data in the set of latches, the one or more managing circuits program a second upper page of data into the second group non-volatile storage elements based on the lower page of data stored in the set of latches, the one or more managing circuits program the second upper page after the one or more managing circuits complete the programming of the first upper page into the first group of non-volatile storage elements.

10. The non-volatile storage device of claim 9, wherein the lower page of data is a first lower page, the one or more managing circuits preserve the first lower page of data in the set of latches while programming a second lower page of data in non-volatile storage elements associated with the second neighbor word line, the one or more managing circuits program the second upper page of data into the second group of non-volatile storage elements based on the preserved first lower page of data.

11. The non-volatile storage device of claim 9, wherein the one or more managing circuits re-program the lower page into the second group of non-volatile storage elements based on the data stored in the set of latches when programming the second upper page of data into the second group non-volatile storage elements based on the lower page stored in the set of latches.

12. The non-volatile storage device of claim 11, wherein the one or more managing circuits use a higher verify level when re-programming the lower page into the second group of non-volatile storage elements compared to when the one or more managing circuits previously programmed the lower page into the second group of non-volatile storage elements.

13. The non-volatile storage device of claim 11, wherein the one or more managing circuits read into the set of latches the lower page data that was re-programmed into the second group of non-volatile storage elements, the one or more managing circuits use the lower page data that was read into the set of latches after the re-programming when programming the upper page of data into the second group non-volatile storage elements.

14. The non-volatile storage device of claim 9, wherein the plurality of data states include an erase state and three programmed states, the first data state is a lowest of the three programmed states.

15. The non-volatile storage device of claim 9, further comprising:

a three-dimensional memory array, the three-dimensional memory array comprising the non-volatile storage elements.

16. The non-volatile storage device of claim 9, wherein each non-volatile storage element of the first group of non-volatile storage elements is part of one of a plurality of NAND strings, each non-volatile storage element of the second group of non-volatile storage elements is part of one of the plurality of NAND strings.

17. A non-volatile storage device, comprising:

a three-dimensional memory array comprising a plurality of non-volatile storage elements.

a set of latches associated with the plurality of non-volatile storage elements;

a plurality of word lines associated with the plurality of non-volatile storage elements, the plurality of word lines including a selected word line, a first neighbor word adjacent to the selected word line and a second neighbor word line adjacent to the selected word line; and

managing circuitry in communication with the plurality of non-volatile storage elements, the set of latches, and the plurality of word lines, the managing circuitry programs a first lower page of data into a first group of the non-volatile storage elements associated with the first neighbor word line, the managing circuitry starts to program a first upper page into the first group of the non-volatile storage elements after programming the first lower page, the first group of non-volatile storage elements are to be programmed to a plurality of data states, the managing circuitry determines when programming of a first data state of the plurality of data states is complete, the managing circuitry pauses programming of the first upper page into the first group of non-volatile storage elements in response to the first data state programming being complete, the managing circuitry reads a second lower page of data from a second group of the non-volatile storage elements associated with the selected word line while the programming is paused, the managing circuitry stores the second lower page of data in the set of latches, the managing circuitry completes the programming of the first upper page into the first group non-volatile storage elements after storing the second lower page of data in the set of latches, the managing circuitry programs a second upper page of data into the second group non-volatile storage elements based on the second lower page of data stored in the set of latches, the managing circuitry programs the second upper page after the managing circuitry completes the programming of the first upper page into the first group of non-volatile storage elements.

18. The non-volatile storage device of claim 17, wherein the managing circuitry preserves the second lower page of data in the set of latches while programming a third lower page of data in non-volatile storage elements associated with the second neighbor word line, the managing circuitry programs the second upper page of data into the second group of non-volatile storage elements based on the preserved second lower page of data.

19. The non-volatile storage device of claim 17, wherein the managing circuitry re-programs the second lower page into the second group of non-volatile storage elements based on the data stored in the set of latches when programming the upper page of data into the second group non-volatile storage elements based on the second lower page stored in the set of latches.

20. The non-volatile storage device of claim 19, wherein the managing circuitry uses a higher verify level when re-programming the second lower page into the second group of non-volatile storage elements compared to when the managing circuitry previously programmed the second lower page into the second group of non-volatile storage elements.