Semiconductor devices

• US 9,053,948 B2
• Filed: 04/18/2014
• Issued: 06/09/2015
• Est. Priority Date: 04/22/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Kyoung-Hee, Lee, Ho-Ki, Choi, Gilheyun, Han, Kyu-Hee, Hong, Jongwon
• Primary Examiner(s): Pham, Long
• Application Number:
  US14/256,232
• Publication Number:
  US 20140312456A1
• Time in Patent Office: 417 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 2221/1047 the air gaps being formed by pores in the dielectric
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.

Claims

1. A semiconductor device, comprising:

wiring lines on a substrate;

an interlayer insulating structure between ones of the wiring lines; and

a cover layer covering the wiring lines and the interlayer insulating structure, wherein the interlayer insulating structure comprises a non-porous layer without pores, a pore-containing layer with pores, and an air gap sequentially provided on the substrate, wherein respective volumes of the pores in the pore-containing layer increase monotonically with increased distance from a surface of the substrate.

2. The device of claim 1, wherein the cover layer comprises a silicon oxycarbide based material.

3. The device of claim 1, wherein the wiring lines comprise tungsten or copper.

4. The device of claim 1, further comprising:

a barrier layer interposed between the substrate and at least one of the wiring lines and between the interlayer insulating structure and the at least one wiring line.

5. The device of claim 4, wherein the at least one wiring line comprises tungsten, and the barrier layer comprises a metal barrier layer.

6. The device of claim 5, wherein the metal barrier layer comprises at least one of tantalum, tantalum nitride, ruthenium, cobalt, manganese, titanium, titanium nitride, tungsten nitride, nickel, nickel boron, or any combination thereof.

7. The device of claim 4, wherein the at least one wiring line comprises copper, and the barrier layer comprises a multi-layered structure including a metal barrier layer and a seed layer on the metal barrier layer.

8. The device of claim 1, further comprising:

an etch stop layer interposed between the substrate and the interlayer insulating structure.

9. The device of claim 8, wherein the etch stop layer comprises silicon carbon nitride.

10. A semiconductor device, comprising:

wiring lines on a substrate; and

an interlayer insulating structure, between ones of the wiring lines, including a pore-containing layer including a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.

11. The device of claim 10 wherein the air gap layer extends substantially completely between the ones of the wiring lines above the pore-containing layer.

12. The device of claim 11 wherein the interlayer insulating structure further comprises a non-porous layer without pores between the pore-containing layer and the substrate.

13. The device of claim 10, further comprising a silicon oxycarbide cover layer covering the wiring lines and the interlayer insulating structure.

14. The device of. Claim 12 wherein the volumes of the pores adjacent the air gap are larger than the volumes of the pores adjacent the non-porous layer.