Compliant printed circuit area array semiconductor device package

• US 9,054,097 B2
• Filed: 05/27/2010
• Issued: 06/09/2015
• Est. Priority Date: 06/02/2009
• Status: Active Grant

• Current Assignee: LCP Medical Technologies Incorporated
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Smith, Bradley K
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US13/266,573
• Publication Number:
  US 20120061846A1
• Time in Patent Office: 1,839 Days
• Field of Search: 257/723, 257/628, 257/724, 257/E21.614
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4867 Applying pastes or inks, e.g. screen printing H01L21/486 takes precedence
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An integrated circuit (IC) package for an IC device, and a method of making the same. The IC package includes an interconnect assembly with at least one printed compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of printed conductive traces electrically coupling a plurality of the first and second contact members. The compliant layer is positioned to bias at least the first contact members against terminals on the IC device. Packaging substantially surrounds the IC device and the interconnect assembly. The second contact members are accessible from outside the packaging.

Claims

1. An integrated circuit (IC) package for an IC device, the IC package comprising:

an interconnect assembly with first and second major surfaces, the interconnect assembly comprising;

a plurality of dielectric layers selectively printed with first and second recesses, the first recesses corresponding to a plurality of first contact members located along the first major surface, a plurality of second contact members located along the second major surface, and a plurality of printed conductive traces electrically coupling a plurality of the first and second contact members;

a conductive material deposited in at least a portion of the first recesses to form the first contact members, the second contact members, and the conductive traces;

a compliant material deposited in the second recesses in the plurality of dielectric layers, the complaint material positioned to bias at least the first contact members against terminals on the IC device; and

packaging substantially surrounding the IC device and the interconnect assembly, wherein the second contact members are accessible from outside the packaging.

2. The IC package of claim 1, wherein the conductive traces create an offset between a plurality of the first contact members relative to a corresponding plurality of the second contact members.

3. The IC package of claim 1, wherein a conductive material, a non-conductive material, and a semi-conductive material are printed on a single layer.

4. The IC package of claim 1, wherein a portion of the compliant material is positioned to bias the second contact members against contact pads on another circuit member.

5. The IC package of claim 1, wherein the interconnect assembly comprises at least one additional circuitry plane, the at least one additional circuitry plane comprises one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, and a flexible circuit.

6. The IC package of claim 1, wherein the dielectric layers comprise a platable material.

7. The IC package of claim 1, wherein the interconnect assembly extends beyond a perimeter edge of the IC package.

8. The IC package of claim 1, further comprising a flexible circuit member electrically coupled to the interconnect assembly that extends beyond a perimeter edge of the IC package.

9. The IC package of claim 1, further comprising at least one electrical device printed on the interconnect assembly and electrically coupled to one or more of the conductive traces, wherein the electrical device is selected from one of shielding, near device decoupling, capacitors, transistors, resistors, filters, signal or power altering and enhancing devices, memory devices, embedded IC, or RF antennae.

10. The IC package of claim 1, further comprising at least one electrical device printed on the packaging.

11. The IC package of claim 1, wherein the packaging comprises one or more of a preformed package, an encapsulating material, or a combination thereof.

29. A method of making an electrical assembly comprising:

electrically coupling the second contact members on the IC package of claim 1 with a printed circuit board.

30. The IC package of claim 1 comprising a plating layer located on the conductive material.

12. An integrated circuit (IC) package for an IC device, the IC package comprising:

an interconnect assembly with first and second major surfaces, the interconnect assembly comprising;

a plurality of dielectric layers selectively printed with first and second recesses, the first recesses corresponding to a plurality of first contact members located along the first major surface, a plurality of second contact members located along the second major surface, and a plurality of printed conductive traces electrically coupling a plurality of the first and second contact members;

a conductive material deposited in at least a portion of the first recesses to form the first contact members, the second contact members, and the conductive traces;

a compliant material deposited in the second recesses in the plurality of dielectric layers positioned to bias at least the first contact members against terminals on the IC device;

at least one IC device with terminals compressively engaged with the first contact members, the compliant layer biasing the first contact members against the terminals on the IC device; and

packaging substantially surrounding the IC device and the interconnect assembly, the second contact members accessible from outside the packaging.

13. The IC package of claim 12 comprising a plating layer located on the conductive material.

14. The IC package of claim 12, wherein the conductive traces create an offset between a plurality of the first contact members relative to a corresponding plurality of the second contact members.

15. The IC package of claim 12, wherein a conductive material, a non-conductive material, and a semi-conductive material are printed on a single layer.

16. The IC package of claim 12, further comprising a plurality of IC devices electrically coupled to the interconnect assembly.

17. The IC package of claim 12, further comprising:

a plurality of interconnect assemblies electrically coupled to one or more of the second contact members; and

a plurality of IC devices each electrically coupled to one of the interconnect assemblies.

18. The IC package of claim 12, further comprising a plurality of electrical devices printed on the interconnect assembly and electrically coupled to one or more of the conductive traces.

19. An electrical system comprising:

the IC package of claim 15; and

a printed circuit board electrically coupled with the second contact members.

20. A method of making an IC package comprising the steps of:

forming an interconnect assembly by

printing at least one dielectric layer onto a surface of a fixture,

depositing a conductive material comprising first contact members,

printing a compliant layer along at least the first contact members,

printing a plurality of conductive traces electrically coupled with one or more of the first contact members,

forming a plurality of second contact members along a second major surface of the interconnect assembly, and

removing the interconnect assembly from the fixture;

compressively engaging terminals on at least one IC device with the first contact members, the compliant layer biasing the first contact members against the terminals on the IC device; and

substantially surrounding the IC device and the interconnect assembly with packaging, the second contact members accessible from outside the packaging.

21. The method of claim 20, wherein the conductive traces comprise substantially rectangular cross-sectional shapes.

22. The method of claim 20, further comprising printing a conductive material, a non-conductive material, and a semi-conductive material on a single layer.

23. The method of claim 20, wherein the step of forming an interconnect assembly further comprises:

depositing the conductive material into a plurality of the cavities in the fixture; and

processing the conductive material to form the plurality of contact members along the first and second major surfaces of the interconnect assembly.

24. The method of claim 20, wherein the step of forming an interconnect assembly further comprises:

printing a second base layer of a dielectric material onto a surface of a fixture;

depositing a conductive material into a plurality of the cavities in the fixture;

processing the conductive material to form a plurality of second contact members; and

coupling the second contact members with the conductive traces on the interconnect assembly so the second contact members extend along the second major surface of the interconnect assembly.

25. The method of claim 20, wherein the step of forming an interconnect assembly further comprises forming at least one additional circuitry plane in the interconnect assembly.

26. The method of claim 20, further comprising electrically coupling a flexible circuit member to the interconnect assembly and extending the flexible circuit member beyond a perimeter edge of the packaging.

27. The method of claim 20, wherein the step of forming an interconnect assembly further comprises:

printing at least one electrical devices on the interconnect assembly; and

electrically coupling the electrical device to at least one contact member.

28. The method of claim 20, wherein the step of forming an interconnect assembly further comprises processing the conductive material, wherein processing comprises one of sintering, plating, or curing.