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Compliant printed circuit area array semiconductor device package

  • US 9,054,097 B2
  • Filed: 05/27/2010
  • Issued: 06/09/2015
  • Est. Priority Date: 06/02/2009
  • Status: Active Grant
First Claim
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1. An integrated circuit (IC) package for an IC device, the IC package comprising:

  • an interconnect assembly with first and second major surfaces, the interconnect assembly comprising;

    a plurality of dielectric layers selectively printed with first and second recesses, the first recesses corresponding to a plurality of first contact members located along the first major surface, a plurality of second contact members located along the second major surface, and a plurality of printed conductive traces electrically coupling a plurality of the first and second contact members;

    a conductive material deposited in at least a portion of the first recesses to form the first contact members, the second contact members, and the conductive traces;

    a compliant material deposited in the second recesses in the plurality of dielectric layers, the complaint material positioned to bias at least the first contact members against terminals on the IC device; and

    packaging substantially surrounding the IC device and the interconnect assembly, wherein the second contact members are accessible from outside the packaging.

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