Method for manufacturing a semiconductor device

• US 9,054,123 B2
• Filed: 11/21/2012
• Issued: 06/09/2015
• Est. Priority Date: 11/21/2012
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Sorschag, Kurt
• Primary Examiner(s): Movva, Amar
• Assistant Examiner(s): Maruf, Sheikh
• Application Number:
  US13/682,995
• Publication Number:
  US 20140141594A1
• Time in Patent Office: 930 Days
• Field of Search: 438/285, 438/259, 438/270, 438/429, 438/580, 438/504, 438/700, 257/494, 257/471, 257/336, 257/331, 257/E21.214, 257/E21.305
• US Class Current: 1/1
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

A method for producing a semiconductor device is provided. The method includes: providing a wafer including an upper surface and a plurality of semiconductor mesas extending to the upper surface; forming a first support structure made of a first material and adjoining the plurality of semiconductor mesas at the upper surface so that adjacent pairs of the plurality of semiconductor mesas are bridged by the first support structure; forming a second support structure made of a second material different from the first material and adjoining the plurality of semiconductor mesas at the upper surface so that the adjacent pairs of the plurality of semiconductor mesas are bridged by the second support structure; removing the first support structure; and at least partly removing the second support structure.

Claims

1. A method for forming a semiconductor device, comprising:

providing a wafer comprising an upper surface and a plurality of semiconductor mesas extending to the upper surface, adjacent pairs of the semiconductor mesas of the plurality of semiconductor mesas being separated from each other by at least one of a trench extending from the upper surface into the wafer, and a non-semiconductor region arranged on a side-wall of the trench;

forming a first support structure comprising a first material above the upper surface and adjoining the plurality of semiconductor mesas at the upper surface so that the adjacent pairs of the semiconductor mesas are bridged by the first support structure;

forming a second support structure comprising a second material above the upper surface and adjoining the plurality of semiconductor mesas at the upper surface so that the adjacent pairs of the semiconductor mesas are bridged by the second support structure, the second material being different from the first material;

removing the first support structure; and

at least partly removing the second support structure.

2. The method of claim 1, wherein the second support structure is formed in a self-adjusted manner with respect to the first support structure.

3. The method of claim 1, wherein forming the second support structure comprises at least one of forming a non-conformal layer of the second material using a CVD-process, and an un-isotropic etching process of the non-conformal layer.

4. The method of claim 1, wherein the second material is selected from a group consisting of a silicon oxide, TEOS, USG, silicon nitride, an imide and silicon.

5. The method of claim 1, wherein the second support structure adjoins the first support structure.

6. The method of claim 1, wherein an extension of the second support structure in a direction which is perpendicular to the upper surface is in a range from about 100 nm to about 5 μ

m.

7. The method of claim 1, wherein forming the first support structure comprises at least one of forming a layer of the first material using a CVD-process in a hydrocarbon atmosphere, and masked etching the layer.

8. The method of claim 1, wherein the first material is selected from a group consisting of carbon, diamond-like carbon, silicon-nitride, an imide, and silicon.

9. The method of claim 1, wherein an extension of the first support structure in a direction which is perpendicular to the upper surface is in a range from about 100 nm to about 5 μ

m.

10. The method of claim 1, wherein at least one of the trench and the non-semiconductor region comprises, in a cross-section which is perpendicular to the upper surface, an aspect ratio of more than about 10.

11. The method of claim 1, further comprising removing the non-semiconductor region after forming the first support structure.

12. The method of claim 11, wherein the second support structure is formed after removing the non-semiconductor region.

13. The method of claim 1, further comprising forming a dielectric layer on the side-wall of the vertical trench prior to at least partly removing the second support structure.

14. The method of claim 13, wherein forming the dielectric layer and removing the first support structure comprise a common oxidation process.

15. The method of claim 1, wherein at least partly removing the second support structure comprises at least one of polishing, etching, and a CMP-process.

16. The method of claim 1, wherein the semiconductor mesas are substantially bar-shaped when seen from above, and wherein the method is performed such that at least one of the first support structure and the second support structure comprise, when seen from above, bar-shaped portions that are tilted with respect to the semiconductor mesas.

17. The method of claim 1, wherein the first support structure is formed as a contiguous mesh.

25. The method of claim 1, wherein the adjacent pairs of the semiconductor mesas are bridged by the first support structure extending over the trench such that the first support structure does not extend into the trench.

26. The method of claim 1, wherein the first and second support structure are formed such that both the first and second support structure simultaneously adjoin the upper surface.

18. A method for forming a TEDFET, comprising:

providing a wafer comprising an upper surface and a semiconductor layer extending to the upper surface;

etching wide trenches from the upper surface into the semiconductor layer to form first semiconductor mesas comprising sidewalls;

forming sacrificial oxide layers on the sidewalls of the first semiconductor mesas;

performing a selective epitaxial growth process to form second semiconductor mesas in the wide trenches between adjacent sacrificial oxide layers;

forming on the upper surface a first support structure of a oxidizable material so that adjacent pairs of the first and second semiconductor mesas are bridged by the first support structure;

removing the sacrificial oxide layers to expose sidewalls of the first and second semiconductor mesas;

forming on the upper surface a second support structure of a non-oxidizable material so that adjacent pairs of the first and second semiconductor mesas are bridged by the second support structure;

thermal oxidizing at least the sidewalls of the first and second semiconductor mesas; and

at least partly removing the second support structure.

19. The method of claim 18, wherein the first support structure is substantially removed during thermal oxidizing at least the sidewalls.

20. A method for forming a semiconductor device, comprising:

providing a wafer comprising an upper surface and a plurality of semiconductor mesas which extend to the upper surface and are, next to the upper surface and in a cross-section which is substantially orthogonal to the upper surface, spaced apart from each other;

forming a first support structure comprising a first material and adjoining the plurality of semiconductor mesas at the upper surface so that adjacent pairs of the semiconductor mesas are bridged by the first support structure and that the first support structure is substantially arranged only above the upper surface;

forming a second support structure comprising a second material and adjoining the plurality of semiconductor mesas at the upper surface so that the adjacent pairs of the semiconductor mesas are bridged by the second support structure and that the second support structure is substantially arranged only above the upper surface, the second material being different from the first material;

processing a side wall of at least one of the plurality of semiconductor mesas;

removing the first support structure; and

at least partly removing the second support structure.

21. The method of claim 20, wherein the wafer is provided with trenches extending from the upper surface into the wafer and between respective pairs of semiconductor mesas.

22. The method of claim 20, wherein the wafer is provided with non-semiconductor regions arranged between respective pairs of semiconductor mesas.

23. The method of claim 20, wherein the second support structure is formed in a self-adjusted manner with respect to the first support structure.

24. The method of claim 20, wherein forming the second support structure comprises at least one of forming a non-conformal layer of the second material using a CVD-process, and a non-isotropic etching process of the non-conformal layer.

27. A method for forming a semiconductor device, comprising:

providing a wafer comprising an upper surface and a plurality of semiconductor mesas extending to the upper surface, adjacent pairs of the semiconductor mesas of the plurality of semiconductor mesas being separated from each other by at least one of a trench extending from the upper surface into the wafer, and a non-semiconductor region arranged on a side-wall of the trench;

forming a first support structure comprising a first material and adjoining the plurality of semiconductor mesas at the upper surface so that the adjacent pairs of the semiconductor mesas are bridged by the first support structure;

forming a second support structure comprising a second material and adjoining the plurality of semiconductor mesas at the upper surface so that the adjacent pairs of the semiconductor mesas are bridged by the second support structure, the second material being different from the first material;

removing the first support structure;

at least partly removing the second support structure; and

removing the non-semiconductor region after forming the first support structure.