Semiconductor device

• US 9,054,154 B2
• Filed: 08/01/2014
• Issued: 06/09/2015
• Est. Priority Date: 10/17/2012
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Onozawa, Yuichi, Yoshimura, Takashi, Takahashi, Hidenori
• Primary Examiner(s): ENAD, CHRISTINE A
• Application Number:
  US14/449,984
• Publication Number:
  US 20140339599A1
• Time in Patent Office: 312 Days
• Field of Search: 257/139, 257/330, 257/565
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/42304 Base electrodes for bipolar transistors
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a first gate electrode that is provided on a first insulating film along one side wall of a first trench and is provided in a second trench, a shield electrode that is provided on a second insulating film along the other side wall of the first trench and is provided in a third trench, a gate runner that is an extended portion of the second trench, has a portion which is provided on the first gate electrode, and is connected to the first gate electrode, and an emitter polysilicon layer that is an extended portion of the third trench, has a portion which is provided on the shield electrode, and is connected to the shield electrode. The semiconductor device has improved turn-on characteristics with a slight increase in the number of process steps, while preventing increase in costs and reduction in yield.

Claims

1. A semiconductor device comprising:

a first trench that is provided in a surface layer of a semiconductor layer of a first conductivity type;

a second trench that is connected to one side wall of the first trench;

a third trench that is connected to the other side wall of the first trench;

a base region of a second conductivity type that is selectively formed in the surface layer of the semiconductor layer along the one side wall of the first trench at a depth that is less than the depth of the first trench;

an emitter region that is formed in a surface layer of the base region so as to come into contact with the side wall of the first trench;

a floating potential region of the second conductivity type that is selectively formed in the surface layer of the semiconductor layer along the other side wall of the first trench;

a first insulating film that is provided along the one side wall of the first trench and an inner wall of the second trench;

a second insulating film that is provided along the other side wall of the first trench and an inner wall of the third trench;

a first gate electrode that is provided on the first insulating film along the one side wall of the first trench and is provided in the second trench;

a shield electrode that is provided on the second insulating film along the other side wall of the first trench and is provided in the third trench;

a third insulating film that fills a space between the first gate electrode and the shield electrode in the first trench;

a gate runner that is an extended portion of the second trench, has a portion which is provided on the first gate electrode, and is connected to the first gate electrode;

an emitter polysilicon layer that is an extended portion of the third trench, has a portion which is provided on the shield electrode, and is connected to the shield electrode;

an interlayer insulating film that covers the first gate electrode, the shield electrode, the emitter region, the gate runner, and the emitter polysilicon layer;

a gate pad that is provided on the interlayer insulating film and is connected to the gate runner; and

an emitter electrode that is provided on the interlayer insulating film so as to be separated from the gate pad and is connected to the emitter region, the base region, and the shield electrode.

2. The semiconductor device according to claim 1, wherein an opening width of the second trench and the third trench is less than an opening width of the first trench.

3. The semiconductor device according to claim 2, wherein an opening width of the first trench is greater than two times the thickness of the first gate electrode.

4. The semiconductor device according to claim 3, further comprising:

a collector layer of the second conductivity type that is provided on a rear surface of the semiconductor; and

a collector electrode that is provided on a surface of the collector layer.

5. The semiconductor device according to claim 2, further comprising:

a collector layer of the second conductivity type that is provided on a rear surface of the semiconductor; and

a collector electrode that is provided on a surface of the collector layer.

6. The semiconductor device according to claim 1, wherein the second trench and the third trench are arranged on the same straight line which traverses the first trench.

7. The semiconductor device according to claim 6, further comprising:

a collector layer of the second conductivity type that is provided on a rear surface of the semiconductor; and

a collector electrode that is provided on a surface of the collector layer.

8. The semiconductor device according to claim 1, wherein a plurality of the second trenches are provided with respect to one third trench, and a portion of the base region which is interposed between adjacent second trenches faces the third trench, with the first trench interposed therebetween.

9. The semiconductor device according to claim 8, further comprising:

a collector layer of the second conductivity type that is provided on a rear surface of the semiconductor; and

a collector electrode that is provided on a surface of the collector layer.

10. The semiconductor device according to claim 1, wherein the second trench and a portion of the first trench form a ring shape in a plan view, and the third trench and a portion of the first trench form a ring shape in a plan view.

11. The semiconductor device according to claim 10, further comprising:

a collector layer of the second conductivity type that is provided on a rear surface of the semiconductor; and

a collector electrode that is provided on a surface of the collector layer.

12. The semiconductor device according to claim 1, wherein a first connection portion between the side wall of the first trench and a side wall of the second trench and a second connection portion between the side wall of the first trench and a side wall of the third trench are chamfered and have a round shape.

13. The semiconductor device according to claim 12, wherein the first connection portion and the second connection portion are not covered with the emitter electrode and the gate pad, respectively.

14. The semiconductor device according to claim 13, further comprising:

a collector layer of the second conductivity type that is provided on a rear surface of the semiconductor; and

a collector electrode that is provided on a surface of the collector layer.

15. The semiconductor device according to claim 12, further comprising:

a collector layer of the second conductivity type that is provided on a rear surface of the semiconductor; and

a collector electrode that is provided on a surface of the collector layer.

16. The semiconductor device according to claim 1, further comprising:

a collector layer of the second conductivity type that is provided on a rear surface of the semiconductor; and

a collector electrode that is provided on a surface of the collector layer.